[llvm] [RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals (PR #94686)

[Philip Reames via llvm-commits]

preames wrote:

Rebased.

There's been some offline discussion here, so let me summarize.

Luke identified a potential miscompile in this patch.  Specifically, the pass 3 emitVSETVLI codepath was previously assuming that if a state was equal in the data flow that the AVL register must hold the same value at runtime.  This was an entirely reasonable assumption with the old data flow (and still is at O3), but becomes unsound after this change.  After offline discussion, a cleanup change was landed as #94340 (which was cut down significantly from prior attempts at this cleanup - the other cases were unreachable code).  This was NFC for the current data flow, but fixes the potential miscompile in this one.  

However, after trying to write test cases to illustrate this change, I think the miscompile above is purely conceptual.  I could not find a way in practice to get the backend to reuse the same register for two different AVLs which is what would be required to hit this.  

Worth noting is that fixing this is a *severe* regression in code quality for the AVLReg case.  This case isn't use for either fixed or scalable vectors.  (Well, fixed could see if for 32+ elements..)   However, intrinsics usage will be hit pretty hard (at O0) for code which uses the vsetvli intrinsic pattern.  I don't think this matters, just noting it for the record.  


https://github.com/llvm/llvm-project/pull/94686