[llvm] d3da134 - [RISCV] Add coverage for vsetvli insertion at O0 [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 17 08:12:18 PDT 2024
Author: Philip Reames
Date: 2024-06-17T07:59:20-07:00
New Revision: d3da134487ca62da09c51ec598798bf8eff027d3
URL: https://github.com/llvm/llvm-project/commit/d3da134487ca62da09c51ec598798bf8eff027d3
DIFF: https://github.com/llvm/llvm-project/commit/d3da134487ca62da09c51ec598798bf8eff027d3.diff
LOG: [RISCV] Add coverage for vsetvli insertion at O0 [nfc]
In review around https://github.com/llvm/llvm-project/pull/94686, we had
a discussion about a possible O0 specific miscompile case without test
coverage. The particular case turned out not be possible to exercise in
practice, but improving our test coverage remains a good idea if we're
going to have differences in the dataflow with and without live intervals.
Added:
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
new file mode 100644
index 0000000000000..aef18fcd06cd6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
@@ -0,0 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
+; RUN: -target-abi=lp64d -verify-machineinstrs -O0 < %s | FileCheck %s
+
+declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
+declare i64 @llvm.riscv.vsetvlimax(i64, i64)
+declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double>,
+ <vscale x 1 x double>,
+ <vscale x 1 x double>,
+ i64, i64)
+declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
+ <vscale x 1 x i64>,
+ ptr,
+ <vscale x 1 x i1>,
+ i64, i64)
+
+define <2 x double> @fixed_length(<2 x double> %a, <2 x double> %b) nounwind {
+; CHECK-LABEL: fixed_length:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: # kill: def $v11 killed $v10
+; CHECK-NEXT: # kill: def $v9 killed $v8
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %1 = fadd <2 x double> %a, %b
+ %2 = fadd <2 x double> %1, %b
+ ret <2 x double> %2
+}
+
+define <vscale x 1 x double> @scalable(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: scalable:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %1 = fadd <vscale x 1 x double> %a, %b
+ %2 = fadd <vscale x 1 x double> %1, %b
+ ret <vscale x 1 x double> %2
+}
+
+
+define <vscale x 1 x double> @intrinsic_same_vlmax(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: intrinsic_same_vlmax:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i64 @llvm.riscv.vsetvlimax(i64 2, i64 7)
+ %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %a,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ ret <vscale x 1 x double> %2
+}
+
+
+define <vscale x 1 x double> @intrinsic_same_avl_imm(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: intrinsic_same_avl_imm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vsetivli a0, 2, e64, m1, tu, ma
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i64 @llvm.riscv.vsetvli(i64 2, i64 2, i64 7)
+ %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %a,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ ret <vscale x 1 x double> %2
+}
+
+define <vscale x 1 x double> @intrinsic_same_avl_reg(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: intrinsic_same_avl_reg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
+ %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %a,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ ret <vscale x 1 x double> %2
+}
+
+define <vscale x 1 x double> @intrinsic_
diff _avl_reg(i64 %avl, i64 %avl2, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: intrinsic_
diff _avl_reg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
+; CHECK-NEXT: # implicit-def: $v9
+; CHECK-NEXT: vfadd.vv v9, v8, v10
+; CHECK-NEXT: vsetvli a0, a1, e64, m1, tu, ma
+; CHECK-NEXT: # implicit-def: $v8
+; CHECK-NEXT: vfadd.vv v8, v9, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
+ %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %a,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %0)
+ %2 = tail call i64 @llvm.riscv.vsetvli(i64 %avl2, i64 2, i64 7)
+ %3 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+ <vscale x 1 x double> undef,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x double> %b,
+ i64 7, i64 %2)
+ ret <vscale x 1 x double> %3
+}
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