[llvm] 52d87de - [Xtensa] Fix register asm parsing. (#95551)

[via llvm-commits]

Author: Andrei Safronov
Date: 2024-06-17T13:26:20+02:00
New Revision: 52d87de7a42d608ac1da33795ca0a892f2b53f36

URL: https://github.com/llvm/llvm-project/commit/52d87de7a42d608ac1da33795ca0a892f2b53f36
DIFF: https://github.com/llvm/llvm-project/commit/52d87de7a42d608ac1da33795ca0a892f2b53f36.diff

LOG: [Xtensa] Fix register asm parsing. (#95551)

Fix passing temporary string object as argument to the StringRef
constructor in "parseRegister" function, because it causes errors in the
test "llvm/test/MC/Xtensa/Core/processor-control.s".

Added: 
    llvm/test/MC/Xtensa/Core/registers.s

Modified: 
    llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index eaf0466302994..b0ce624a495fd 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -572,7 +572,7 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands,
   case AsmToken::Integer:
     if (!SR)
       return ParseStatus::NoMatch;
-    RegName = StringRef(std::to_string(getLexer().getTok().getIntVal()));
+    RegName = getLexer().getTok().getString();
     RegNo = MatchRegisterName(RegName);
     if (RegNo == 0)
       RegNo = MatchRegisterAltName(RegName);

diff  --git a/llvm/test/MC/Xtensa/Core/registers.s b/llvm/test/MC/Xtensa/Core/registers.s
new file mode 100644
index 0000000000000..bf6499c7abde1
--- /dev/null
+++ b/llvm/test/MC/Xtensa/Core/registers.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align	4
+LBL0:
+
+#############################################################
+## Check special registers parsing
+#############################################################
+
+# CHECK-INST: xsr a8, sar
+# CHECK: encoding: [0x80,0x03,0x61]
+xsr a8, 3