[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads and Stores (PR #84965)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 11 16:56:41 PDT 2024
================
@@ -648,6 +683,51 @@ bool RISCVLegalizerInfo::legalizeExt(MachineInstr &MI,
return true;
}
+bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ MachineRegisterInfo &MRI = *MIB.getMRI();
+ MachineFunction *MF = MI.getParent()->getParent();
+ const DataLayout &DL = MIB.getDataLayout();
+ LLVMContext &Ctx = MF->getFunction().getContext();
+
+ Register DstReg = MI.getOperand(0).getReg();
+ Register PtrReg = MI.getOperand(1).getReg();
+ LLT LoadTy = MRI.getType(DstReg);
+
+ assert(MI.hasOneMemOperand() &&
+ "Load instructions only have one MemOperand.");
+ Align Alignment = (*MI.memoperands_begin())->getAlign();
+ MachineMemOperand *LoadMMO = MF->getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad, LoadTy, Alignment);
+
+ const auto *TLI = STI.getTargetLowering();
+ EVT VT = EVT::getEVT(getTypeForLLT(LoadTy, Ctx));
+
+ if (TLI->allowsMemoryAccessForAlignment(Ctx, DL, VT, *LoadMMO))
+ return true;
+
+ unsigned EltSizeBits = LoadTy.getScalarSizeInBits();
+ assert((EltSizeBits == 16 || EltSizeBits == 32 || EltSizeBits == 64) &&
+ "Unexpected unaligned RVV load type");
+
+ // Calculate the new vector type with i8 elements
+ unsigned NumElements =
+ LoadTy.getElementCount().getKnownMinValue() * (EltSizeBits / 8);
+ LLT NewLoadTy = LLT::scalable_vector(NumElements, 8);
+
+ DstOp NewDstReg(NewLoadTy);
+ MachineMemOperand *NewLoadMMO = MF->getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad, NewLoadTy, Alignment);
+
+ auto NewLoad = MIB.buildLoad(NewDstReg, PtrReg, *NewLoadMMO);
----------------
michaelmaitland wrote:
I think you are using this function for both load and store but the logic in it is only assuming it is legalizing a load.
https://github.com/llvm/llvm-project/pull/84965
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