[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads and Stores (PR #84965)

[Michael Maitland via llvm-commits]

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@@ -648,6 +683,51 @@ bool RISCVLegalizerInfo::legalizeExt(MachineInstr &MI,
   return true;
 }
 
+bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
+                                           MachineIRBuilder &MIB) const {
+  MachineRegisterInfo &MRI = *MIB.getMRI();
+  MachineFunction *MF = MI.getParent()->getParent();
+  const DataLayout &DL = MIB.getDataLayout();
+  LLVMContext &Ctx = MF->getFunction().getContext();
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register PtrReg = MI.getOperand(1).getReg();
+  LLT LoadTy = MRI.getType(DstReg);
+
+  assert(MI.hasOneMemOperand() &&
+         "Load instructions only have one MemOperand.");
+  Align Alignment = (*MI.memoperands_begin())->getAlign();
+  MachineMemOperand *LoadMMO = MF->getMachineMemOperand(
+      MachinePointerInfo(), MachineMemOperand::MOLoad, LoadTy, Alignment);
----------------
michaelmaitland wrote:

Should we be casting the original MI to [GLoad](https://llvm.org/doxygen/classllvm_1_1GLoad.html) and building the MachineMemOperand using existing info. It looks like RISCVTargetLowering::ExpandUnalignedRVVLoad uses the mem operand from the original load.

https://github.com/llvm/llvm-project/pull/84965