[llvm] [RFC][MC] Cache MCRegAliasIterator (PR #93510)

[Pierre van Houtryve via llvm-commits]

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@@ -726,60 +730,122 @@ class MCRegUnitRootIterator {
 /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
 /// set, Reg itself is included in the list.  This iterator does not guarantee
 /// any ordering or that entries are unique.
+///
+/// This iterator can work in two modes: cached and uncached.
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Pierre-vh wrote:

I did that first because I assumed we'd like a killswitch of some kind for targets where the cache doesn't help, but if I read the compile time tracker diff correctly, it seems to be a universal win so I'll revisit it and split up the implementation
![image](https://github.com/llvm/llvm-project/assets/29600849/48ea789b-4e4c-4a74-8df6-b800541275e2)


https://github.com/llvm/llvm-project/pull/93510