[llvm] [RFC][MC] Cache MCRegAliasIterator (PR #93510)

[Nikita Popov via llvm-commits]

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@@ -726,60 +730,122 @@ class MCRegUnitRootIterator {
 /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
 /// set, Reg itself is included in the list.  This iterator does not guarantee
 /// any ordering or that entries are unique.
+///
+/// This iterator can work in two modes: cached and uncached.
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nikic wrote:

The fact that cached and uncached implementations are interleaved in one class seems pretty awkward. Might it make sense to only expose the cached version here and have the uncached version inside getCachedAliasesOf() only?

https://github.com/llvm/llvm-project/pull/93510