[llvm] [AArch64] Replace AND with LSL#2 for LDR target (#34101) (PR #89531)

[via llvm-commits]

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@@ -16918,6 +16918,24 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
     return (!C1 || !C2 || C1->getZExtValue() >= C2->getZExtValue());
   }
 
+  // We do not need to fold when this shifting used in specific load case:
+  // (ldr x, (add x, (shl (srl x, c1) 2)))
+  if (N->getOpcode() == ISD::SHL) {
+    auto C2 = dyn_cast_or_null<ConstantSDNode>(N->getOperand(1));
+    if (C2 && C2->getZExtValue() == 2) {
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ParkHanbum wrote:

@davemgreen As I understand it, this is why `(shl (srl x, c1) 2))` is generated. The example C code presented in the issue is as follows.

```
int test(unsigned long long a, unsigned long long b, int *table) {    
  return table[(a * b) >> 58];  
}
```

The above code creates `(shr x, 58)`.
It then makes it `(shl (shr x, 58), 2)`, which is shift-lefted to address 4 bit. This is probably why the value is fixed at 2 in 32-bit addressing mode. 

If there are other addressing modes, I suppose this value could change, but I haven't test of them yet. should do I?


https://github.com/llvm/llvm-project/pull/89531