[llvm] [AArch64] Replace AND with LSL#2 for LDR target (#34101) (PR #89531)

[David Green via llvm-commits]

================
@@ -16918,6 +16918,24 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
     return (!C1 || !C2 || C1->getZExtValue() >= C2->getZExtValue());
   }
 
+  // We do not need to fold when this shifting used in specific load case:
+  // (ldr x, (add x, (shl (srl x, c1) 2)))
+  if (N->getOpcode() == ISD::SHL) {
+    auto C2 = dyn_cast_or_null<ConstantSDNode>(N->getOperand(1));
+    if (C2 && C2->getZExtValue() == 2) {
----------------
davemgreen wrote:

Oh - should the shift amount match the loaded type? So if it is loading an i32 like the tests, it should be 2, but if it was loading i16/i64 it would need to be different shift amounts?

https://github.com/llvm/llvm-project/pull/89531