[llvm] [RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (PR #93735)

[Craig Topper via llvm-commits]

topperc wrote:

> > According to our performance measurements
> 
> Shouldn't this latency be determined by the CPU pipeline? Why do we need measurements?

Yes. We got it from our internal microarchitectural specification document. Min did confirm it with measurements though. An earlier version said 6 cycles and it was changed later.

https://github.com/llvm/llvm-project/pull/93735