[llvm] [RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (PR #93735)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> According to our performance measurements

Shouldn't this latency be determined by the CPU pipeline? Why do we need measurements?

https://github.com/llvm/llvm-project/pull/93735