[llvm] [RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) -> (bitcast (sra (v2Xi16 (bitcast X)), 15)) (PR #93565)

[Philip Reames via llvm-commits]

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@@ -13704,6 +13704,44 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
+// Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) ->
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preames wrote:

I'm wondering if we could generalize this slightly.

mul (and X, 0x10001), 0xfffff is simply a sext(trunc (bitcast to i16) to i1).  That operation can be done via a pair of shifts.  At that point, I think the lshr/shl pair fold in this case.

We could also use demanded bits in place of the actual and node.  

https://github.com/llvm/llvm-project/pull/93565