[llvm] [AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (PR #92130)

[via llvm-commits]

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@@ -657,8 +657,8 @@ bool AArch64PostLegalizerCombiner::optimizeConsecutiveMemOpAddressing(
         Register PtrBaseReg;
         APInt Offset;
         LLT StoredValTy = MRI.getType(St->getValueReg());
-        unsigned ValSize = StoredValTy.getSizeInBits();
-        if (ValSize < 32 || St->getMMO().getSizeInBits() != ValSize)
+        const auto ValSize = StoredValTy.getSizeInBits();
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Him188 wrote:

Done, replaced with a bail-out check for operand 0 being scalable vector.


https://github.com/llvm/llvm-project/pull/92130