[llvm] [AMDGPU] Reserved private memory register during PEI (PR #93536)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: None (PankajDwivedi-25)

<details>
<summary>Changes</summary>

- Reserved newly selected private memory registers in entry Function Prologue generation.
- Added assertion patch in eliminateFrameIndex to ensure register scavenger do not choose them.

---
Full diff: https://github.com/llvm/llvm-project/pull/93536.diff


2 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIFrameLowering.cpp (+1) 
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+3) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index eae666ab0e7d7..97a8ff4486609 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -579,6 +579,7 @@ Register SIFrameLowering::getEntryFunctionReservedScratchRsrcReg(
         (!GITPtrLoReg || !TRI->isSubRegisterEq(Reg, GITPtrLoReg))) {
       MRI.replaceRegWith(ScratchRsrcReg, Reg);
       MFI->setScratchRSrcReg(Reg);
+      MRI.reserveReg(Reg, TRI);
       return Reg;
     }
   }
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ddb5f71935685..e718bad9ba837 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2083,6 +2083,9 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
 
   assert(SPAdj == 0 && "unhandled SP adjustment in call sequence?");
 
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  assert(MRI.isReserved(MFI->getScratchRSrcReg()));
+
   MachineOperand &FIOp = MI->getOperand(FIOperandNum);
   int Index = MI->getOperand(FIOperandNum).getIndex();
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/93536