[llvm] [WIP] Implemented a patch to optimize SGPR spills. (PR #93509)

[Matt Arsenault via llvm-commits]

================
@@ -152,6 +154,14 @@ namespace {
       AU.addRequired<MachineBlockFrequencyInfo>();
       AU.addPreserved<MachineBlockFrequencyInfo>();
       AU.addPreservedID(MachineDominatorsID);
+
+      /// NOTE: As in AMDGPU pass pipeline, reg alloc is spillted into 2 phases
----------------
arsenm wrote:

```suggestion
      /// NOTE: In AMDGPU pass pipeline, reg alloc is split into 2 phases
```

https://github.com/llvm/llvm-project/pull/93509