[llvm] [SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (PR #91871)

[Yingwei Zheng via llvm-commits]

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@@ -0,0 +1,776 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @scmp(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    setg %cl
+; CHECK-NEXT:    movl $255, %eax
+; CHECK-NEXT:    cmovgel %ecx, %eax
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-NEXT:    retq
+  %1 = call i8 @llvm.scmp(i32 %x, i32 %y)
+  ret i8 %1
+}
+
+define i4 @scmp_narrow_result(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp_narrow_result:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    setg %cl
+; CHECK-NEXT:    movl $255, %eax
+; CHECK-NEXT:    cmovgel %ecx, %eax
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-NEXT:    retq
+  %1 = call i4 @llvm.scmp(i32 %x, i32 %y)
+  ret i4 %1
+}
+
+define i8 @scmp_narrow_op(i62 %x, i62 %y) {
+; CHECK-LABEL: scmp_narrow_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shlq $2, %rsi
+; CHECK-NEXT:    sarq $2, %rsi
+; CHECK-NEXT:    shlq $2, %rdi
+; CHECK-NEXT:    sarq $2, %rdi
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    setg %cl
+; CHECK-NEXT:    movl $255, %eax
+; CHECK-NEXT:    cmovgel %ecx, %eax
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-NEXT:    retq
+  %1 = call i8 @llvm.scmp(i62 %x, i62 %y)
+  ret i8 %1
+}
+
+define i141 @scmp_wide_result(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp_wide_result:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    setg %cl
+; CHECK-NEXT:    movq $-1, %rax
+; CHECK-NEXT:    cmovgeq %rcx, %rax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    retq
+  %1 = call i141 @llvm.scmp(i32 %x, i32 %y)
+  ret i141 %1
+}
+
+define i8 @scmp_wide_op(i109 %x, i109 %y) {
+; CHECK-LABEL: scmp_wide_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shlq $19, %rsi
+; CHECK-NEXT:    sarq $19, %rsi
+; CHECK-NEXT:    shlq $19, %rcx
+; CHECK-NEXT:    sarq $19, %rcx
+; CHECK-NEXT:    cmpq %rdi, %rdx
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    sbbq %rsi, %rax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    movzbl %al, %r8d
+; CHECK-NEXT:    cmpq %rdx, %rdi
+; CHECK-NEXT:    sbbq %rcx, %rsi
+; CHECK-NEXT:    movl $255, %eax
+; CHECK-NEXT:    cmovgel %r8d, %eax
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-NEXT:    retq
+  %1 = call i8 @llvm.scmp(i109 %x, i109 %y)
+  ret i8 %1
+}
+
+define i41 @scmp_uncommon_types(i7 %x, i7 %y) {
+; CHECK-LABEL: scmp_uncommon_types:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addb %sil, %sil
+; CHECK-NEXT:    sarb %sil
+; CHECK-NEXT:    addb %dil, %dil
+; CHECK-NEXT:    sarb %dil
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    setg %cl
+; CHECK-NEXT:    movq $-1, %rax
+; CHECK-NEXT:    cmovgeq %rcx, %rax
+; CHECK-NEXT:    retq
+  %1 = call i41 @llvm.scmp(i7 %x, i7 %y)
+  ret i41 %1
+}
+
+define <4 x i32> @scmp_normal_vectors(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: scmp_normal_vectors:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[3,3,3,3]
+; CHECK-NEXT:    movd %xmm2, %eax
+; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT:    movd %xmm2, %ecx
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    cmpl %eax, %ecx
+; CHECK-NEXT:    setg %dl
+; CHECK-NEXT:    movl $-1, %eax
+; CHECK-NEXT:    cmovll %eax, %edx
+; CHECK-NEXT:    movd %edx, %xmm2
+; CHECK-NEXT:    pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT:    movd %xmm3, %ecx
+; CHECK-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; CHECK-NEXT:    movd %xmm3, %edx
+; CHECK-NEXT:    xorl %esi, %esi
+; CHECK-NEXT:    cmpl %ecx, %edx
+; CHECK-NEXT:    setg %sil
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    movd %esi, %xmm3
+; CHECK-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT:    movd %xmm1, %ecx
+; CHECK-NEXT:    movd %xmm0, %edx
+; CHECK-NEXT:    xorl %esi, %esi
+; CHECK-NEXT:    cmpl %ecx, %edx
+; CHECK-NEXT:    setg %sil
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    movd %esi, %xmm2
+; CHECK-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; CHECK-NEXT:    movd %xmm1, %ecx
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; CHECK-NEXT:    movd %xmm0, %edx
+; CHECK-NEXT:    xorl %esi, %esi
+; CHECK-NEXT:    cmpl %ecx, %edx
+; CHECK-NEXT:    setg %sil
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    movd %esi, %xmm0
+; CHECK-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; CHECK-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %1 = call <4 x i32> @llvm.scmp(<4 x i32> %x, <4 x i32> %y)
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dtcxzyw wrote:

It is surprising that we can omit mangling suffix here :)



https://github.com/llvm/llvm-project/pull/91871