[llvm] [SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (PR #91871)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 27 09:18:42 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: None (Poseydon42)
<details>
<summary>Changes</summary>
This PR adds initial support for the `scmp`/`ucmp` 3-way comparison intrinsics in the SelectionDAG.
What works as of now:
* An invokation of the intrinsic in the IR gets properly lowered into SelectionDAG
* A node with opcodes `UCMP`/`SCMP` gets properly expanded into two comparisons and two selects
* Narrow scalar arguments and return types are properly handled (i.e. i3 or i51)
* Wide scalar arguments and return types are properly handled (i.e. i87 or i139)
* Vector arguments and return types are properly widened/split where necessary
---
Patch is 95.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/91871.diff
14 Files Affected:
- (modified) llvm/include/llvm/CodeGen/ISDOpcodes.h (+6)
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+4)
- (modified) llvm/include/llvm/Target/TargetSelectionDAG.td (+5)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (+6)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+41)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (+10)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (+2)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+142)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+16)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (+2)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+21)
- (modified) llvm/lib/CodeGen/TargetLoweringBase.cpp (+3)
- (added) llvm/test/CodeGen/X86/scmp.ll (+776)
- (added) llvm/test/CodeGen/X86/ucmp.ll (+1010)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 6429947958ee9..7d36f582244b0 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -677,6 +677,12 @@ enum NodeType {
UMIN,
UMAX,
+ /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
+ /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
+ /// different to the result.
+ SCMP,
+ UCMP,
+
/// Bitwise operators - logical and, logical or, logical xor.
AND,
OR,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 7ed08cfa8a202..82c450afcbcf6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5402,6 +5402,10 @@ class TargetLowering : public TargetLoweringBase {
/// method accepts integers as its arguments.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
+ /// Method for building the DAG expansion of ISD::[US]CMP. This
+ /// method accepts integers as its arguments
+ SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
+
/// Method for building the DAG expansion of ISD::[US]SHLSAT. This
/// method accepts integers as its arguments.
SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 1684b424e3b44..6d771521aa739 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -434,6 +434,11 @@ def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def scmp : SDNode<"ISD::SCMP" , SDTIntBinOp,
+ []>;
+def ucmp : SDNode<"ISD::UCMP" , SDTIntBinOp,
+ []>;
+
def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bfc3e08c1632d..f7da195e03bd1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1148,6 +1148,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
+ case ISD::SCMP:
+ case ISD::UCMP:
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -3864,6 +3866,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::USUBSAT:
Results.push_back(TLI.expandAddSubSat(Node, DAG));
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Results.push_back(TLI.expandCMP(Node, DAG));
+ break;
case ISD::SSHLSAT:
case ISD::USHLSAT:
Results.push_back(TLI.expandShlSat(Node, DAG));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0aa36deda79dc..e82ab9db4c090 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -232,6 +232,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = PromoteIntRes_CMP(N);
+ break;
+
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -1246,6 +1251,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
+SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
+ EVT PromotedResultTy =
+ TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), PromotedResultTy,
+ N->getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
SDValue Mask = N->getOperand(0);
@@ -1874,6 +1886,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::ROTL:
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
+
case ISD::FSHL:
case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
@@ -2184,6 +2199,17 @@ SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
ZExtPromotedInteger(N->getOperand(1))), 0);
}
+SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
+ SDValue LHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(0))
+ : SExtPromotedInteger(N->getOperand(0));
+ SDValue RHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(1))
+ : SExtPromotedInteger(N->getOperand(1));
+
+ return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS), 0);
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
ZExtPromotedInteger(N->getOperand(2))), 0);
@@ -2741,6 +2767,9 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
+ case ISD::SCMP:
+ case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
+
case ISD::ADD:
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
@@ -3233,6 +3262,11 @@ void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
SplitInteger(Result, Lo, Hi);
}
+void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue ExpandedCMP = TLI.expandCMP(N, DAG);
+ SplitInteger(ExpandedCMP, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue &Lo, SDValue &Hi) {
SDLoc dl(N);
@@ -5137,6 +5171,9 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::RETURNADDR:
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
+
case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
case ISD::STACKMAP:
Res = ExpandIntOp_STACKMAP(N, OpNo);
@@ -5398,6 +5435,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
}
+SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
+ return TLI.expandCMP(N, DAG);
+}
+
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 4b06e19656ce6..74ab2f44149fa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -324,6 +324,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_Overflow(SDNode *N);
SDValue PromoteIntRes_FFREXP(SDNode *N);
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_CMP(SDNode *N);
SDValue PromoteIntRes_Select(SDNode *N);
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
SDValue PromoteIntRes_SETCC(SDNode *N);
@@ -375,6 +376,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_Shift(SDNode *N);
+ SDValue PromoteIntOp_CMP(SDNode *N);
SDValue PromoteIntOp_FunnelShift(SDNode *N);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
@@ -457,6 +459,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CMP (SDNode *N, SDValue &Lo, SDValue &Hi);
+
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -485,6 +489,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ExpandIntOp_SETCC(SDNode *N);
SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
SDValue ExpandIntOp_Shift(SDNode *N);
+ SDValue ExpandIntOp_CMP(SDNode *N);
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
SDValue ExpandIntOp_XINT_TO_FP(SDNode *N);
@@ -779,6 +784,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
+ SDValue ScalarizeVecRes_CMP(SDNode *N);
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
@@ -852,6 +858,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void SplitVectorResult(SDNode *N, unsigned ResNo);
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_FFREXP(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi);
void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -915,6 +922,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SplitVecOp_VSETCC(SDNode *N);
SDValue SplitVecOp_FP_ROUND(SDNode *N);
SDValue SplitVecOp_FPOpDifferentTypes(SDNode *N);
+ SDValue SplitVecOp_CMP(SDNode *N);
SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SplitVecOp_VP_CttzElements(SDNode *N);
@@ -982,6 +990,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecRes_Ternary(SDNode *N);
SDValue WidenVecRes_Binary(SDNode *N);
+ SDValue WidenVecRes_CMP(SDNode *N);
SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
SDValue WidenVecRes_StrictFP(SDNode *N);
@@ -1001,6 +1010,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
+ SDValue WidenVecOp_CMP(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 423df9ae6b2a5..3a1c11da24075 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -442,6 +442,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
case ISD::MGATHER:
+ case ISD::SCMP:
+ case ISD::UCMP:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
case ISD::SMULFIX:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cab4dc5f3c156..0fe6e9e0252a4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -164,6 +164,12 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ROTR:
R = ScalarizeVecRes_BinOp(N);
break;
+
+ case ISD::SCMP:
+ case ISD::UCMP:
+ R = ScalarizeVecRes_CMP(N);
+ break;
+
case ISD::FMA:
case ISD::FSHL:
case ISD::FSHR:
@@ -213,6 +219,27 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS, N->getFlags());
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_CMP(SDNode *N) {
+ SDLoc DL(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ if (getTypeAction(LHS.getValueType()) ==
+ TargetLowering::TypeScalarizeVector) {
+ LHS = GetScalarizedVector(LHS);
+ RHS = GetScalarizedVector(RHS);
+ } else {
+ EVT VT = LHS.getValueType().getVectorElementType();
+ LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
+ DAG.getVectorIdxConstant(0, DL));
+ RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
+ DAG.getVectorIdxConstant(0, DL));
+ }
+
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ N->getValueType(0).getVectorElementType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
SDValue Op1 = GetScalarizedVector(N->getOperand(1));
@@ -1184,6 +1211,10 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SplitVecRes_TernaryOp(N, Lo, Hi);
break;
+ case ISD::SCMP: case ISD::UCMP:
+ SplitVecRes_CMP(N, Lo, Hi);
+ break;
+
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
case ISD::STRICT_##DAGN:
#include "llvm/IR/ConstrainedOps.def"
@@ -1327,6 +1358,21 @@ void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
{Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
}
+void DAGTypeLegalizer::SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT SplitResVT = N->getValueType(0).getHalfNumVectorElementsVT(Ctxt);
+
+ auto [LHSLo, LHSHi] = DAG.SplitVector(LHS, dl);
+ auto [RHSLo, RHSHi] = DAG.SplitVector(RHS, dl);
+
+ Lo = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSLo, RHSLo);
+ Hi = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSHi, RHSHi);
+}
+
void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
@@ -3054,6 +3100,11 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
Res = SplitVecOp_FPOpDifferentTypes(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = SplitVecOp_CMP(N);
+ break;
+
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
@@ -4043,6 +4094,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_FPOpDifferentTypes(SDNode *N) {
return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
}
+SDValue DAGTypeLegalizer::SplitVecOp_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
+ GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
+
+ EVT ResVT = N->getValueType(0);
+ ElementCount SplitOpEC = LHSLo.getValueType().getVectorElementCount();
+ EVT NewResVT =
+ EVT::getVectorVT(Ctxt, ResVT.getVectorElementType(), SplitOpEC);
+
+ SDValue Lo = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSLo, RHSLo);
+ SDValue Hi = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSHi, RHSHi);
+
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
+}
+
SDValue DAGTypeLegalizer::SplitVecOp_FP_TO_XINT_SAT(SDNode *N) {
EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
@@ -4220,6 +4290,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
Res = WidenVecRes_Binary(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecRes_CMP(N);
+ break;
+
case ISD::FPOW:
case ISD::FREM:
if (unrollExpandedOp())
@@ -4426,6 +4501,42 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
{InOp1, InOp2, Mask, N->getOperand(3)}, N->getFlags());
}
+SDValue DAGTypeLegalizer::WidenVecRes_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ EVT OpElementVT = OpVT.getVectorElementType();
+ EVT TransformedOpVT = TLI.getTypeToTransformTo(Ctxt, OpVT);
+ if (TransformedOpVT.getVectorNumElements() > OpVT.getVectorNumElements()) {
+ LHS = GetWidenedVector(LHS);
+ RHS = GetWidenedVector(RHS);
+ }
+
+ EVT WidenResVT = TLI.getTypeToTransformTo(Ctxt, N->getValueType(0));
+ ElementCount WidenResEC = WidenResVT.getVectorElementCount();
+ EVT WidenResElementVT = WidenResVT.getVectorElementType();
+
+ SDValue CMP = DAG.getNode(N->getOpcode(), dl, LHS.getValueType(), LHS, RHS);
+
+ EVT WideUndefVectorVT = EVT::getVectorVT(Ctxt, OpElementVT, WidenResEC);
+ SDValue WideUndefValue = DAG.getUNDEF(WideUndefVectorVT);
+
+ SDValue WideResult =
+ DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideUndefVectorVT, WideUndefValue,
+ CMP, DAG.getVectorIdxConstant(0, dl));
+
+ ISD::NodeType ExtendCode;
+ if (OpElementVT.getSizeInBits() > WidenResElementVT.getSizeInBits()) {
+ ExtendCode = ISD::TRUNCATE;
+ } else {
+ ExtendCode = (N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND);
+ }
+ return DAG.getNode(ExtendCode, dl, WidenResVT, WideResult);
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_BinaryWithExtraScalarOp(SDNode *N) {
// Binary op widening, but with an extra operand that shouldn't be widened.
SDLoc dl(N);
@@ -6129,6 +6240,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
Res = WidenVecOp_EXTEND(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecOp_CMP(N);
+ break;
+
case ISD::FP_EXTEND:
case ISD::STRICT_FP_EXTEND:
case ISD::FP_ROUND:
@@ -6273,6 +6389,32 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
}
}
+SDValue DAGTypeLegalizer::WidenVecOp_CMP(SDNode *N) {
+ SDLoc dl(N);
+
+ EVT OpVT = N->getOperand(0).getValueType();
+ EVT ResVT = N->getValueType(0);
+ SDValue LHS = GetWidenedVector(N->getOperand(0));
+ SDValue RHS = GetWidenedVector(N->getOperand(1));
+
+ // 1. EXTRACT_SUBVECTOR
+ // 2. SIGN_EXTEND/ZERO_EXTEND
+ // 3. CMP
+ LHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, LHS,
+ DAG.getVectorIdxConstant(0, dl));
+ RHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, RHS,
+ DAG.getVectorIdxConstant(0, dl));
+
+ // At this point the result type is guaranteed to be valid, so we can use it
+ // as the operand type by extending it appropriately
+ ISD::NodeType ExtendOpcode =
+ N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ LHS = DAG.getNode(ExtendOpcode, dl, ResVT, LHS);
+ RHS = DAG.getNode(ExtendOpcode, dl, ResVT, RHS);
+
+ return DAG.getNode(N->getOpcode(), dl, ResVT, LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::WidenVecOp_UnrollVectorOp(SDNode *N) {
// The result (and first input) is legal, but the second input is illegal.
// We can't do much to fix that, so just unroll and let the extracts off of
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index cfd82a342433f..16d8a9816b013 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7143,6 +7143,22 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
return;
}
+ case Intrinsic::scmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ I.getType());
+ setValue(&I, DAG.getNode(ISD::SCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
+ case Intrinsic::ucmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/91871
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