[clang] [llvm] [AMDGPU][WIP] Extend permlane16, permlanex16 and permlane64 intrinsic lowering for generic types (PR #92725)

[Vikram Hegde via llvm-commits]

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@@ -5433,7 +5450,16 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
                             ? Src0
                             : B.buildBitcast(LLT::scalar(Size), Src0).getReg(0);
     Src0 = B.buildAnyExt(S32, Src0Cast).getReg(0);
-    if (Src2.isValid()) {
+
+    if (IsPermLane16) {
+      Register Src1Cast =
+          MRI.getType(Src1).isScalar()
+              ? Src1
+              : B.buildBitcast(LLT::scalar(Size), Src2).getReg(0);
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vikramRH wrote:

Yes, I will take over the changes from https://github.com/llvm/llvm-project/pull/89217 once finalized,

https://github.com/llvm/llvm-project/pull/92725