[llvm] 1d3329c - [Thumb] Resolve FIXME: Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" (#82120)
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Sun May 26 11:58:36 PDT 2024
Author: AtariDreams
Date: 2024-05-26T14:58:32-04:00
New Revision: 1d3329c2e82166be9b60921a8a571ed3c279c028
URL: https://github.com/llvm/llvm-project/commit/1d3329c2e82166be9b60921a8a571ed3c279c028
DIFF: https://github.com/llvm/llvm-project/commit/1d3329c2e82166be9b60921a8a571ed3c279c028.diff
LOG: [Thumb] Resolve FIXME: Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" (#82120)
Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" if
"c1 >> c2" is a cheaper immediate than "c1" using
HasLowerConstantMaterializationCost
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb/shift-and.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 73f8bda9a0214..5090d8bf6cf22 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14381,9 +14381,17 @@ static SDValue CombineANDShift(SDNode *N,
}
}
- // FIXME: Transform "(and (shl x, c2) c1)" ->
- // "(shl (and x, c1>>c2), c2)" if "c1 >> c2" is a cheaper immediate than
- // c1.
+ // Transform "(and (shl x, c2) c1)" into "(shl (and x, c1>>c2), c2)"
+ // if "c1 >> c2" is a cheaper immediate than "c1"
+ if (LeftShift &&
+ HasLowerConstantMaterializationCost(C1 >> C2, C1, Subtarget)) {
+
+ SDValue And = DAG.getNode(ISD::AND, DL, MVT::i32, N0->getOperand(0),
+ DAG.getConstant(C1 >> C2, DL, MVT::i32));
+ return DAG.getNode(ISD::SHL, DL, MVT::i32, And,
+ DAG.getConstant(C2, DL, MVT::i32));
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/Thumb/shift-and.ll b/llvm/test/CodeGen/Thumb/shift-and.ll
index e5fee86343b0e..a8a09dbe1b739 100644
--- a/llvm/test/CodeGen/Thumb/shift-and.ll
+++ b/llvm/test/CodeGen/Thumb/shift-and.ll
@@ -70,9 +70,8 @@ define i32 @test6(i32 %x) {
; CHECK-LABEL: test6:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
-; CHECK-NEXT: lsls r1, r1, #29
-; CHECK-NEXT: lsls r0, r0, #29
-; CHECK-NEXT: ands r0, r1
+; CHECK-NEXT: ands r1, r0
+; CHECK-NEXT: lsls r0, r1, #29
; CHECK-NEXT: bx lr
entry:
%0 = shl i32 %x, 29
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