[llvm] 9a038fc - [RISCV] PseudoMovImm is not a IsSignExtendingOpW instruction.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-05-24T14:45:58-07:00
New Revision: 9a038fceb3fae8e77c0118633866c04d6de4407b

URL: https://github.com/llvm/llvm-project/commit/9a038fceb3fae8e77c0118633866c04d6de4407b
DIFF: https://github.com/llvm/llvm-project/commit/9a038fceb3fae8e77c0118633866c04d6de4407b.diff

LOG: [RISCV] PseudoMovImm is not a IsSignExtendingOpW instruction.

We only know it expands to a 2 instruction sequence, not necessarily
a sign extended sequence.

Happened to notice while I was looking at naming for the proposed
rematerializable LUI+ADDI for addresses.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9d574edb4e6d1..ce50fe6e2cbb0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1560,8 +1560,8 @@ def PseudoJump : Pseudo<(outs GPR:$rd), (ins pseudo_jump_symbol:$target), [],
 // -riscv-use-rematerializable-movimm in RISCVISelDAGToDAG.cpp
 // It will be expanded after register allocation.
 // FIXME: The scheduling information does not reflect the multiple instructions.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 1,
-    isPseudo = 1, isReMaterializable = 1, IsSignExtendingOpW = 1 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
+    isReMaterializable = 1 in
 def PseudoMovImm : Pseudo<(outs GPR:$dst), (ins i32imm:$imm), []>,
                    Sched<[WriteIALU]>;