[llvm] abc4c21 - [X86] Add test case for #93000
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 24 07:43:03 PDT 2024
Author: Simon Pilgrim
Date: 2024-05-24T15:42:47+01:00
New Revision: abc4c21ce470bd3a3029ad11b6e4be190464acd6
URL: https://github.com/llvm/llvm-project/commit/abc4c21ce470bd3a3029ad11b6e4be190464acd6
DIFF: https://github.com/llvm/llvm-project/commit/abc4c21ce470bd3a3029ad11b6e4be190464acd6.diff
LOG: [X86] Add test case for #93000
Added:
llvm/test/CodeGen/X86/pr93000.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/pr93000.ll b/llvm/test/CodeGen/X86/pr93000.ll
new file mode 100644
index 0000000000000..97c17f2ec2dc6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr93000.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=x86_64- -mcpu=x86-64-v4 | FileCheck %s
+
+define void @PR93000(ptr %a0, ptr %a1, ptr %a2, <32 x i16> %a3) {
+; CHECK-LABEL: PR93000:
+; CHECK: # %bb.0: # %Entry
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: addq $4, %rdi
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_1: # %Loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: kmovd %eax, %k1
+; CHECK-NEXT: notl %eax
+; CHECK-NEXT: kmovd %eax, %k2
+; CHECK-NEXT: vpblendmw (%rsi), %zmm0, %zmm1 {%k1}
+; CHECK-NEXT: vmovdqu16 (%rdx), %zmm1 {%k2}
+; CHECK-NEXT: vmovdqu64 %zmm1, (%rsi)
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: addq $4, %rdi
+; CHECK-NEXT: testl %eax, %eax
+; CHECK-NEXT: jne .LBB0_1
+; CHECK-NEXT: # %bb.2: # %Then
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+Entry:
+ %pre = load i32, ptr %a0, align 4
+ br label %Loop
+
+Loop: ; preds = %Loop, %Entry
+ %p = phi i32 [ %limit, %Loop ], [ %pre, %Entry ]
+ %lsr.iv.pn = phi ptr [ %lsr.iv, %Loop ], [ %a0, %Entry ]
+ %lsr.iv = getelementptr i8, ptr %lsr.iv.pn, i64 4
+ %pn = xor i32 %p, -1
+ %m = bitcast i32 %p to <32 x i1>
+ %mn = bitcast i32 %pn to <32 x i1>
+ %mload0 = tail call <32 x i16> @llvm.masked.load.v32i16.p0(ptr %a1, i32 2, <32 x i1> %m, <32 x i16> %a3)
+ %mload1 = tail call <32 x i16> @llvm.masked.load.v32i16.p0(ptr %a2, i32 2, <32 x i1> %mn, <32 x i16> %mload0)
+ store <32 x i16> %mload1, ptr %a1, align 2
+ %limit = load i32, ptr %lsr.iv, align 4
+ %icmp = icmp eq i32 %limit, 0
+ br i1 %icmp, label %Then, label %Loop
+
+Then: ; preds = %Loop
+ ret void
+}
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