[llvm] [PowerPC] option `-msoft-float` should not block the PC-relative address instruction (PR #92543)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Fri May 24 07:39:55 PDT 2024
https://github.com/diggerlin updated https://github.com/llvm/llvm-project/pull/92543
>From 8b0f5313ce8a2111f6b7ddd960523c916c51e646 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 16 May 2024 15:24:57 -0400
Subject: [PATCH 1/4] fixed the issue
https://github.com/llvm/llvm-project/issues/62372
---
llvm/lib/Target/PowerPC/PPC.td | 3 +-
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +-
llvm/lib/Target/PowerPC/PPCInstrP10.td | 84 ++++++++++++--------
llvm/test/CodeGen/PowerPC/issue-62372-bug.ll | 15 ++++
4 files changed, 70 insertions(+), 38 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index b962ed28d7200..31441fd4f0d6b 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -296,8 +296,7 @@ def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
"true",
"Enable prefixed instructions",
- [FeatureISA3_0, FeatureP8Vector,
- FeatureP9Altivec]>;
+ [FeatureISA3_1]>;
def FeaturePCRelativeMemops :
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d27932f2915fb..855927ec8b3ed 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -18258,9 +18258,11 @@ unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
FlagSet |= PPC::MOF_SubtargetBeforeP9;
else {
FlagSet |= PPC::MOF_SubtargetP9;
- if (Subtarget.hasPrefixInstrs())
- FlagSet |= PPC::MOF_SubtargetP10;
}
+
+ if (Subtarget.hasPrefixInstrs())
+ FlagSet |= PPC::MOF_SubtargetP10;
+
if (Subtarget.hasSPE())
FlagSet |= PPC::MOF_SubtargetSPE;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 5f2937d47a519..b76f1419df778 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -654,13 +654,10 @@ let Predicates = [PrefixInstrs] in {
(ins s34imm:$SI),
"pli $RT, $SI", IIC_IntSimple, []>;
}
+}
+let Predicates = [PrefixInstrs, HasFPU] in {
let mayLoad = 1, mayStore = 0 in {
- defm PLXV :
- 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
- "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
defm PLFS :
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
@@ -671,6 +668,28 @@ let Predicates = [PrefixInstrs] in {
(ins (memri34_pcrel $D, $RA):$addr),
(ins s34imm_pcrel:$D), "plfd $RST, $addr",
"plfd $RST, $D", IIC_LdStLFD>;
+ }
+ let mayStore = 1, mayLoad = 0 in {
+ defm PSTFS :
+ MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
+ (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
+ (ins f4rc:$RST, s34imm_pcrel:$D),
+ "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
+ defm PSTFD :
+ MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
+ (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
+ (ins f8rc:$RST, s34imm_pcrel:$D),
+ "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
+ }
+}
+
+let Predicates = [PrefixInstrs, HasP10Vector] in {
+ let mayLoad = 1, mayStore = 0 in {
+ defm PLXV :
+ 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
defm PLXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
@@ -683,6 +702,28 @@ let Predicates = [PrefixInstrs] in {
(ins s34imm_pcrel:$D),
"plxsd $RST, $addr", "plxsd $RST, $D",
IIC_LdStLFD>;
+ }
+ let mayStore = 1, mayLoad = 0 in {
+ defm PSTXV :
+ 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
+ (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
+ (ins vsrc:$XST, s34imm_pcrel:$D),
+ "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
+ defm PSTXSSP :
+ 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
+ (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
+ defm PSTXSD :
+ 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
+ (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
+ }
+}
+
+let Predicates = [PrefixInstrs] in {
+ let mayLoad = 1, mayStore = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
@@ -745,31 +786,6 @@ let Predicates = [PrefixInstrs] in {
}
let mayStore = 1, mayLoad = 0 in {
- defm PSTXV :
- 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
- (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
- (ins vsrc:$XST, s34imm_pcrel:$D),
- "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
- defm PSTFS :
- MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
- (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins f4rc:$RST, s34imm_pcrel:$D),
- "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
- defm PSTFD :
- MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
- (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins f8rc:$RST, s34imm_pcrel:$D),
- "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
- defm PSTXSSP :
- 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
- (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins vfrc:$RST, s34imm_pcrel:$D),
- "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
- defm PSTXSD :
- 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
- (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins vfrc:$RST, s34imm_pcrel:$D),
- "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PSTB8 :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
@@ -1136,7 +1152,7 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
[]>;
}
-let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
+let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
defm PLXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
@@ -1145,7 +1161,7 @@ let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] i
IIC_LdStLFD>;
}
-let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
+let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
defm PSTXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
(ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
@@ -1157,7 +1173,7 @@ let Predicates = [PairedVectorMemops] in {
// Intrinsics for Paired Vector Loads.
def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
- let Predicates = [PairedVectorMemops, PrefixInstrs] in {
+ let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
}
// Intrinsics for Paired Vector Stores.
@@ -1165,7 +1181,7 @@ let Predicates = [PairedVectorMemops] in {
(STXVP $XSp, memrix16:$dst)>;
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
(STXVPX $XSp, XForm:$dst)>;
- let Predicates = [PairedVectorMemops, PrefixInstrs] in {
+ let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
(PSTXVP $XSp, memri34:$dst)>;
}
diff --git a/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll b/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
new file mode 100644
index 0000000000000..12c4afc56cdb8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
@@ -0,0 +1,15 @@
+; RUN: llc -o - %s| FileCheck %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+ at bar = dso_local global i32 0, align 4
+
+define dso_local ptr @foo() #0 {
+entry:
+ ret ptr @bar
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr10" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+mma,+paired-vector-memops,+pcrelative-memops,+power10-vector,+power8-vector,+power9-vector,+prefix-instrs,+quadword-atomics,+vsx,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-hard-float,-htm,-privileged,-rop-protect,-spe" "use-soft-float"="true" }
+
+
+; CHECK: paddi 3, 0, bar at PCREL, 1
>From d7e3be0e14ffdd328a45211d4f3060103df1b465 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Tue, 21 May 2024 15:01:58 -0400
Subject: [PATCH 2/4] address comment
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 13 +++---
llvm/lib/Target/PowerPC/PPCInstrP10.td | 45 +++++++++++++-------
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +-
llvm/test/CodeGen/PowerPC/issue-62372-bug.ll | 15 -------
llvm/test/CodeGen/PowerPC/pr92543.ll | 15 +++++++
5 files changed, 51 insertions(+), 39 deletions(-)
delete mode 100644 llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
create mode 100644 llvm/test/CodeGen/PowerPC/pr92543.ll
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 855927ec8b3ed..fe487147be331 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -9402,7 +9402,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
// double. This is to exploit the XXSPLTIDP instruction.
// If we lose precision, we use XXSPLTI32DX.
if (BVNIsConstantSplat && (SplatBitSize == 64) &&
- Subtarget.hasPrefixInstrs()) {
+ Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
// Check the type first to short-circuit so we don't modify APSplatBits if
// this block isn't executed.
if ((Op->getValueType(0) == MVT::v2f64) &&
@@ -9547,11 +9547,11 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
// with 4-byte splats. We replicate the SplatBits in case of 2-byte splat to
// make a 4-byte splat element. For example: 2-byte splat of 0xABAB can be
// turned into a 4-byte splat of 0xABABABAB.
- if (Subtarget.hasPrefixInstrs() && SplatSize == 2)
+ if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 2)
return getCanonicalConstSplat(SplatBits | (SplatBits << 16), SplatSize * 2,
Op.getValueType(), DAG, dl);
- if (Subtarget.hasPrefixInstrs() && SplatSize == 4)
+ if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector() && SplatSize == 4)
return getCanonicalConstSplat(SplatBits, SplatSize, Op.getValueType(), DAG,
dl);
@@ -10184,7 +10184,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
}
- if (Subtarget.hasPrefixInstrs()) {
+ if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
SDValue SplatInsertNode;
if ((SplatInsertNode = lowerToXXSPLTI32DX(SVOp, DAG)))
return SplatInsertNode;
@@ -17672,7 +17672,7 @@ bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
return false;
case MVT::f32:
case MVT::f64: {
- if (Subtarget.hasPrefixInstrs()) {
+ if (Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
// we can materialize all immediatess via XXSPLTI32DX and XXSPLTIDP.
return true;
}
@@ -18256,9 +18256,8 @@ unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
// Compute subtarget flags.
if (!Subtarget.hasP9Vector())
FlagSet |= PPC::MOF_SubtargetBeforeP9;
- else {
+ else
FlagSet |= PPC::MOF_SubtargetP9;
- }
if (Subtarget.hasPrefixInstrs())
FlagSet |= PPC::MOF_SubtargetP10;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index b76f1419df778..2fd5978a23c80 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -1252,6 +1252,9 @@ let Predicates = [PCRelativeMemops] in {
def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
(PSTDpc $RS, $ga, 0)>;
+}
+
+let Predicates = [PCRelativeMemops, HasFPU] in {
// Load f32
def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
@@ -1268,6 +1271,11 @@ let Predicates = [PCRelativeMemops] in {
def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
(PSTFDpc $FRS, $ga, 0)>;
+ def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
+ (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
+}
+
+let Predicates = [PCRelativeMemops, HasP10Vector] in {
// Load f128
def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),
(COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
@@ -1304,6 +1312,14 @@ let Predicates = [PCRelativeMemops] in {
def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
(PSTXVpc $XS, $ga, 0)>;
+ // Special Cases For PPCstore_scal_int_from_vsr
+ def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
+ (PSTXSDpc $src, $dst, 0)>;
+ def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
+ (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
+}
+
+let Predicates = [PCRelativeMemops] in {
// Atomic Load
def : Pat<(i32 (atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga))),
(PLBZpc $ga, 0)>;
@@ -1330,15 +1346,6 @@ let Predicates = [PCRelativeMemops] in {
def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
(PSTDpc $RS, $ga, 0)>;
- // Special Cases For PPCstore_scal_int_from_vsr
- def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
- (PSTXSDpc $src, $dst, 0)>;
- def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
- (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
-
- def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
- (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
-
// If the PPCmatpcreladdr node is not caught by any other pattern it should be
// caught here and turned into a paddi instruction to materialize the address.
def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
@@ -1351,7 +1358,7 @@ let Predicates = [PCRelativeMemops] in {
(PADDI8 $in, $addr)>;
}
-let Predicates = [PrefixInstrs] in {
+let Predicates = [PrefixInstrs, HasP10Vector] in {
def XXPERMX :
8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC, u3imm:$IMM),
@@ -2158,7 +2165,7 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
class xxevalPattern <dag pattern, bits<8> imm> :
Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
-let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
+let AddedComplexity = 400, Predicates = [PrefixInstrs, HasP10Vector] in {
def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
i32immNonAllOneNonZero:$A,
i32immNonAllOneNonZero:$A,
@@ -2295,7 +2302,7 @@ def : Pat<(f64 nzFPImmAsi64:$A),
(PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>;
}
-let Predicates = [PrefixInstrs] in {
+let Predicates = [PrefixInstrs, HasP10Vector] in {
def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
@@ -2316,7 +2323,9 @@ let Predicates = [PrefixInstrs] in {
(XXBLENDVW $A, $B, $C)>;
def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
(XXBLENDVD $A, $B, $C)>;
+}
+let Predicates = [PrefixInstrs] in {
// Anonymous patterns to select prefixed loads and stores.
// Load i32
def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
@@ -2351,7 +2360,9 @@ let Predicates = [PrefixInstrs] in {
def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
+}
+let Predicates = [PrefixInstrs, HasFPU] in {
// Load / Store f32
def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
@@ -2361,7 +2372,13 @@ let Predicates = [PrefixInstrs] in {
(COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
+ // Prefixed fpext to v2f64
+ def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
+ (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
+
+}
+let Predicates = [PrefixInstrs] in {
// Atomic Load
def : Pat<(i32 (atomic_load_8 PDForm:$src)), (PLBZ memri34:$src)>;
def : Pat<(i32 (atomic_load_16 PDForm:$src)), (PLHZ memri34:$src)>;
@@ -2373,10 +2390,6 @@ let Predicates = [PrefixInstrs] in {
def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>;
def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>;
def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>;
-
- // Prefixed fpext to v2f64
- def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
- (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
}
def InsertEltShift {
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7e4cd6c72aa87..9e8da59615dfb 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1695,7 +1695,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// transform it to the prefixed version so we don't have to use the XForm.
if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
(!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
- Subtarget.hasPrefixInstrs()) {
+ Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
MI.setDesc(TII.get(NewOpc));
OpC = NewOpc;
diff --git a/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll b/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
deleted file mode 100644
index 12c4afc56cdb8..0000000000000
--- a/llvm/test/CodeGen/PowerPC/issue-62372-bug.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc -o - %s| FileCheck %s
-
-target triple = "powerpc64le-unknown-linux-gnu"
-
- at bar = dso_local global i32 0, align 4
-
-define dso_local ptr @foo() #0 {
-entry:
- ret ptr @bar
-}
-
-attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr10" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+mma,+paired-vector-memops,+pcrelative-memops,+power10-vector,+power8-vector,+power9-vector,+prefix-instrs,+quadword-atomics,+vsx,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-hard-float,-htm,-privileged,-rop-protect,-spe" "use-soft-float"="true" }
-
-
-; CHECK: paddi 3, 0, bar at PCREL, 1
diff --git a/llvm/test/CodeGen/PowerPC/pr92543.ll b/llvm/test/CodeGen/PowerPC/pr92543.ll
new file mode 100644
index 0000000000000..ca4ae398c63cd
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr92543.ll
@@ -0,0 +1,15 @@
+; RUN: llc -ppc-asm-full-reg-names -o - %s| FileCheck %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+ at bar = dso_local global i32 0, align 4
+
+define dso_local ptr @foo() #0 {
+entry:
+ ret ptr @bar
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "target-cpu"="pwr10" "target-features"="+altivec,+isa-v30-instructions,+isa-v31-instructions,+pcrelative-memops,+power10-vector,+power9-vector,+prefix-instrs,+vsx,-hard-float" "use-soft-float"="true" }
+
+
+; CHECK: paddi r3, 0, bar at PCREL, 1
>From a8f25025b88c36414eb63ab16f1c22138d8c1753 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 23 May 2024 10:26:55 -0400
Subject: [PATCH 3/4] address comment
---
llvm/test/CodeGen/PowerPC/pr62372.ll | 12 ++++++++++++
llvm/test/CodeGen/PowerPC/pr92543.ll | 15 ---------------
2 files changed, 12 insertions(+), 15 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/pr62372.ll
delete mode 100644 llvm/test/CodeGen/PowerPC/pr92543.ll
diff --git a/llvm/test/CodeGen/PowerPC/pr62372.ll b/llvm/test/CodeGen/PowerPC/pr62372.ll
new file mode 100644
index 0000000000000..7e32727519d66
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr62372.ll
@@ -0,0 +1,12 @@
+; RUN: llc -ppc-asm-full-reg-names -mcpu=pwr10 -mtriple powerpc64le-unknown-linux-gnu -o - %s| FileCheck %s
+
+ at bar = dso_local global i32 0, align 4
+
+define dso_local ptr @foo() #0 {
+entry:
+ ret ptr @bar
+}
+
+attributes #0 = { "use-soft-float"="true" }
+
+; CHECK: paddi r3, 0, bar at PCREL, 1
diff --git a/llvm/test/CodeGen/PowerPC/pr92543.ll b/llvm/test/CodeGen/PowerPC/pr92543.ll
deleted file mode 100644
index ca4ae398c63cd..0000000000000
--- a/llvm/test/CodeGen/PowerPC/pr92543.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc -ppc-asm-full-reg-names -o - %s| FileCheck %s
-
-target triple = "powerpc64le-unknown-linux-gnu"
-
- at bar = dso_local global i32 0, align 4
-
-define dso_local ptr @foo() #0 {
-entry:
- ret ptr @bar
-}
-
-attributes #0 = { noinline nounwind optnone uwtable "target-cpu"="pwr10" "target-features"="+altivec,+isa-v30-instructions,+isa-v31-instructions,+pcrelative-memops,+power10-vector,+power9-vector,+prefix-instrs,+vsx,-hard-float" "use-soft-float"="true" }
-
-
-; CHECK: paddi r3, 0, bar at PCREL, 1
>From 6b4bead269aaec4c43b650a10673cf9d38f2ba8b Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Fri, 24 May 2024 10:09:01 -0400
Subject: [PATCH 4/4] split test case command into two line
---
llvm/test/CodeGen/PowerPC/pr62372.ll | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/PowerPC/pr62372.ll b/llvm/test/CodeGen/PowerPC/pr62372.ll
index 7e32727519d66..8df236adc92d7 100644
--- a/llvm/test/CodeGen/PowerPC/pr62372.ll
+++ b/llvm/test/CodeGen/PowerPC/pr62372.ll
@@ -1,4 +1,5 @@
-; RUN: llc -ppc-asm-full-reg-names -mcpu=pwr10 -mtriple powerpc64le-unknown-linux-gnu -o - %s| FileCheck %s
+; RUN: llc -ppc-asm-full-reg-names -mcpu=pwr10 -mtriple powerpc64le-unknown-linux-gnu \
+; RUN: -o - %s | FileCheck %s
@bar = dso_local global i32 0, align 4
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