[llvm] Promote the Pseudo Opcode of instructions that deduce the sign extension for extsw from 32 bits to 64 bits when eliminating the extsw instruction in PPCMIPeepholes optimization. (PR #85451)

[Amy Kwan via llvm-commits]

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@@ -5234,6 +5234,219 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
 const unsigned MAX_BINOP_DEPTH = 1;
+
+// The function will promote the instruction which defines the register `Reg`
+// in the parameter from a 32-bit to a 64-bit instruction if needed. The logic
+// used to check whether an instruction needs to be promoted or not is similar
+// to the logic used to check a defined register whether is isSignOrZeroExtended
+// or not in the function PPCInstrInfo::isSignOrZeroExtended. The
+// `PromoteInstr32To64ForEmliEXTSW` function is recursive. The parameter
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amy-kwan wrote:

```suggestion
// This function will promote the instruction which defines the register `Reg`
// in the parameter from a 32-bit to a 64-bit instruction if needed. The logic
// used to check whether an instruction needs to be promoted or not is similar
// to the logic used to check whether or not a defined register is sign or zero extended
// within the function PPCInstrInfo::isSignOrZeroExtended. Additionally, the
// `PromoteInstr32To64ForElimEXTSW` function is recursive. 
```

https://github.com/llvm/llvm-project/pull/85451