[llvm] [polly] [test]: fix filecheck annotation typos (PR #91854)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 06:46:40 PDT 2024
https://github.com/klensy updated https://github.com/llvm/llvm-project/pull/91854
>From fbc3212e3c18e8a24432eac6079e29bc84cb146c Mon Sep 17 00:00:00 2001
From: klensy <klensy at users.noreply.github.com>
Date: Sat, 11 May 2024 14:26:52 +0300
Subject: [PATCH 1/4] llvm: fix few typos in filecheck tests and few more
---
.../AArch64/sve-shuffle-broadcast.ll | 2 +-
.../irreducible/diverged-entry-headers.ll | 2 +-
llvm/test/CodeGen/AArch64/arm64_32-atomics.ll | 20 +++++++++----------
...tliner-retaddr-sign-diff-scope-same-key.ll | 2 +-
.../stp-opt-with-renaming-undef-assert.mir | 2 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 ++--
llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 2 +-
.../test/CodeGen/Mips/optimizeAndPlusShift.ll | 18 ++++++++---------
.../intel-usm-addrspaces.ll | 2 +-
llvm/test/CodeGen/SystemZ/prefetch-04.ll | 2 +-
llvm/test/CodeGen/X86/global-sections.ll | 4 ++--
llvm/test/CodeGen/X86/tailregccpic.ll | 4 ++--
.../InstrRef/livedebugvalues_illegal_locs.mir | 6 +++---
llvm/test/MC/ARM/coff-relocations.s | 2 +-
llvm/test/MC/Mips/expansion-jal-sym-pic.s | 12 +++++------
.../Transforms/Inline/update_invoke_prof.ll | 2 +-
.../InstCombine/lifetime-sanitizer.ll | 2 +-
llvm/test/Transforms/LoopUnroll/peel-loop2.ll | 2 +-
llvm/test/Transforms/LoopVectorize/memdep.ll | 2 +-
...wrapping-pointer-non-integral-addrspace.ll | 2 +-
.../X86/good-prototype.ll | 2 +-
llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 2 +-
llvm/test/tools/llvm-ar/replace-update.test | 2 +-
23 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
index a2526d9f5591a..c2aab35194831 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll
@@ -31,7 +31,7 @@ define void @broadcast() #0{
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
-; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
index 335026dc9b62b..efad77b684a75 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
@@ -90,7 +90,7 @@ S:
br i1 %cond.uni, label %exit, label %T
T:
-; CHECK-NIT: DIVERGENT: %tt.phi = phi i32
+; CHECK-NOT: DIVERGENT: %tt.phi = phi i32
%tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
%tt = add i32 %b, 1
br label %P
diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
index 0000262e833da..19b9205dc1786 100644
--- a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
@@ -2,70 +2,70 @@
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
define i8 @test_load_8(ptr %addr) {
-; CHECK-LABAL: test_load_8:
+; CHECK-LABEL: test_load_8:
; CHECK: ldarb w0, [x0]
%val = load atomic i8, ptr %addr seq_cst, align 1
ret i8 %val
}
define i16 @test_load_16(ptr %addr) {
-; CHECK-LABAL: test_load_16:
+; CHECK-LABEL: test_load_16:
; CHECK: ldarh w0, [x0]
%val = load atomic i16, ptr %addr acquire, align 2
ret i16 %val
}
define i32 @test_load_32(ptr %addr) {
-; CHECK-LABAL: test_load_32:
+; CHECK-LABEL: test_load_32:
; CHECK: ldar w0, [x0]
%val = load atomic i32, ptr %addr seq_cst, align 4
ret i32 %val
}
define i64 @test_load_64(ptr %addr) {
-; CHECK-LABAL: test_load_64:
+; CHECK-LABEL: test_load_64:
; CHECK: ldar x0, [x0]
%val = load atomic i64, ptr %addr seq_cst, align 8
ret i64 %val
}
define ptr @test_load_ptr(ptr %addr) {
-; CHECK-LABAL: test_load_ptr:
+; CHECK-LABEL: test_load_ptr:
; CHECK: ldar w0, [x0]
%val = load atomic ptr, ptr %addr seq_cst, align 8
ret ptr %val
}
define void @test_store_8(ptr %addr) {
-; CHECK-LABAL: test_store_8:
+; CHECK-LABEL: test_store_8:
; CHECK: stlrb wzr, [x0]
store atomic i8 0, ptr %addr seq_cst, align 1
ret void
}
define void @test_store_16(ptr %addr) {
-; CHECK-LABAL: test_store_16:
+; CHECK-LABEL: test_store_16:
; CHECK: stlrh wzr, [x0]
store atomic i16 0, ptr %addr seq_cst, align 2
ret void
}
define void @test_store_32(ptr %addr) {
-; CHECK-LABAL: test_store_32:
+; CHECK-LABEL: test_store_32:
; CHECK: stlr wzr, [x0]
store atomic i32 0, ptr %addr seq_cst, align 4
ret void
}
define void @test_store_64(ptr %addr) {
-; CHECK-LABAL: test_store_64:
+; CHECK-LABEL: test_store_64:
; CHECK: stlr xzr, [x0]
store atomic i64 0, ptr %addr seq_cst, align 8
ret void
}
define void @test_store_ptr(ptr %addr) {
-; CHECK-LABAL: test_store_ptr:
+; CHECK-LABEL: test_store_ptr:
; CHECK: stlr wzr, [x0]
store atomic ptr null, ptr %addr seq_cst, align 8
ret void
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
index a5757a70843a9..fa63df35ac857 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
}
define void @b() "sign-return-address"="non-leaf" {
-; CHECK-LABE: b: // @b
+; CHECK-LABEL: b: // @b
; V8A-NOT: hint #25
; V83A-NOT: paciasp
; CHECK-NOT: .cfi_negate_ra_state
diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
index 66d2067b531a3..bfdb1763776b4 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
@@ -12,7 +12,7 @@
# This test also checks that pairwise store STP is generated.
-# CHECK-LABLE: test
+# CHECK-LABEL: test
# CHECK: bb.0:
# CHECK-NEXT: liveins: $x0, $x17, $x18
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 50423c59eabe9..526d5c946ec7f 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
}
; no-op
-; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
ret void
}
-; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
+; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
index 9fb64471e9881..892e66aed4e5f 100644
--- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -22,7 +22,7 @@
; CHECK-DEFAULT: ldr{{.*}}, #4]
; CHECK-DEFAULT: str{{.*}}, #4]
; CHECK-DEFAULT: ldr{{.*}}, #8]!
-; CHECK-DEAFULT: ldr{{.*}}, #8]!
+; CHECK-DEFAULT: ldr{{.*}}, #8]!
; CHECK-DEFAULT: str{{.*}}, #8]!
; CHECK-COMPLEX: ldr{{.*}}, #8]!
diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
index bf69adf6702f0..58920483e24bf 100644
--- a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
+++ b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
@@ -3,11 +3,11 @@
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
define i32 @shl_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: shl_32:
+; MIPS32-LABEL: shl_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: sllv $2, $4, $5
-; MIPS64-LABLE: shl_32:
+; MIPS64-LABEL: shl_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
}
define i32 @lshr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: lshr_32:
+; MIPS32-LABEL: lshr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srlv $2, $4, $5
-; MIPS64-LABLE: lshr_32:
+; MIPS64-LABEL: lshr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
}
define i32 @ashr_32(i32 %a, i32 %b) {
-; MIPS32-LABLE: ashr_32:
+; MIPS32-LABEL: ashr_32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: srav $2, $4, $5
-; MIPS64-LABLE: ashr_32:
+; MIPS64-LABEL: ashr_32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: sll $2, $4, 0
@@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
}
define i64 @shl_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: shl_64:
+; MIPS64-LABEL: shl_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
@@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
}
define i64 @lshr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: lshr_64:
+; MIPS64-LABEL: lshr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
@@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
}
define i64 @ashr_64(i64 %a, i64 %b) {
-; MIPS64-LABLE: ashr_64:
+; MIPS64-LABEL: ashr_64:
; MIPS64: # %bb.0:
; MIPS64-NEXT: sll $1, $5, 0
; MIPS64-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
index b5df462bd8fa9..f5f1382a35fca 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
@@ -6,7 +6,7 @@
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-: Capability USMStorageClassesINTEL
-; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL
+; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL
; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]]
; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]]
; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]]
diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll
index 61a2a1460c583..10755bdb66eb5 100644
--- a/llvm/test/CodeGen/SystemZ/prefetch-04.ll
+++ b/llvm/test/CodeGen/SystemZ/prefetch-04.ll
@@ -6,7 +6,7 @@
;
; CHECK-LABEL: for.body
; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1
-; CHECK-not: call void @llvm.prefetch
+; CHECK-NOT: call void @llvm.prefetch
define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {
entry:
diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll
index b300fc87e38ab..0175eb23ce080 100644
--- a/llvm/test/CodeGen/X86/global-sections.ll
+++ b/llvm/test/CodeGen/X86/global-sections.ll
@@ -36,8 +36,8 @@ bb5:
}
; LINUX: .size F2,
-; LINUX-NEX: .cfi_endproc
-; LINUX-NEX: .section .rodata,"a", at progbits
+; LINUX-NEXT: .cfi_endproc
+; LINUX-NEXT: .section .rodata,"a", at progbits
; LINUX-SECTIONS: .section .text.F2,"ax", at progbits
; LINUX-SECTIONS: .size F2,
diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll
index f89c4ac4df599..a3a17d3b05397 100644
--- a/llvm/test/CodeGen/X86/tailregccpic.ll
+++ b/llvm/test/CodeGen/X86/tailregccpic.ll
@@ -13,12 +13,12 @@ entry:
ret void
}
-;CHECK-LABLE: tail_call_regcall:
+;CHECK-LABEL: tail_call_regcall:
;CHECK: # %bb.0:
;CHECK-NEXT: jmp __regcall3__func # TAILCALL
;CHECK-NEXT: .Lfunc_end0:
-;CHECK-LABLE: __regcall3__func:
+;CHECK-LABEL: __regcall3__func:
;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
;CHECK-NEXT: movl a0 at GOT(%ecx), %ecx
;CHECK-NEXT: movl %eax, (%ecx)
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
index d4ed0fba2d7cd..60c3d32595ea5 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -43,7 +43,7 @@ debugValueSubstitutions:
body: |
bb.0.entry:
successors: %bb.1, %bb.2
- ; CHECK-LABE: bb.0.entry:
+ ; CHECK-LABEL: bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
@@ -69,8 +69,8 @@ body: |
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
;;; Test non-def operand
- ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
- ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
+ ;; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+ ;; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s
index 5225b5e656762..16993cf7a8588 100644
--- a/llvm/test/MC/ARM/coff-relocations.s
+++ b/llvm/test/MC/ARM/coff-relocations.s
@@ -25,7 +25,7 @@ branch24t_1:
bl target
@ CHECK-ENCODING-LABEL: <branch24t_1>:
-@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0
+@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0
.thumb_func
branch20t:
diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
index c7b5ccc1880bd..1279de10d2503 100644
--- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
@@ -227,12 +227,12 @@ local_label:
# XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label
# ELF-XO32: 3c 19 00 00 lui $25, 0
-# ELF-XO32-MEXT: R_MIPS_CALL_HI16 weak_label
-# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp
-# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25)
-# ELF-XO32-MEXT: R_MIPS_CALL_LO16 weak_label
-# ELF-XO32-MEXT: 03 20 f8 09 jalr $25
-# ELF-XO32-MEXT: R_MIPS_JALR weak_label
+# ELF-XO32-NEXT: R_MIPS_CALL_HI16 weak_label
+# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp
+# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25)
+# ELF-XO32-NEXT: R_MIPS_CALL_LO16 weak_label
+# ELF-XO32-NEXT: 03 20 f8 09 jalr $25
+# ELF-XO32-NEXT: R_MIPS_JALR weak_label
# N32: lw $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A]
# N32: # fixup A - offset: 0, value: %call16(weak_label), kind: fixup_Mips_CALL16
diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll
index f6b86dfe5bb1b..b5fb669c93cbd 100644
--- a/llvm/test/Transforms/Inline/update_invoke_prof.ll
+++ b/llvm/test/Transforms/Inline/update_invoke_prof.ll
@@ -66,7 +66,7 @@ ret:
; CHECK: invoke void @callee2(
; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]]
-; CHECK-LABL: @callee(
+; CHECK-LABEL: @callee(
; CHECK: invoke void %func(
; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]]
; CHECK: invoke void @callee1(
diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
index e379b32b45734..62573398fc16a 100644
--- a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
+++ b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll
@@ -56,7 +56,7 @@ entry:
call void @llvm.lifetime.start.p0(i64 1, ptr %text)
call void @llvm.lifetime.end.p0(i64 1, ptr %text)
- ; CHECK-NO: call void @llvm.lifetime
+ ; CHECK-NOT: call void @llvm.lifetime
call void @foo(ptr %text) ; Keep alloca alive
diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
index a732984d697ad..754e0d32cc1d0 100644
--- a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
+++ b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll
@@ -32,7 +32,7 @@ for.end:
ret void
}
-; CHECK_LABEL: @funca
+; CHECK-LABEL: @funca
; Peeled iteration
; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma
diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll
index b891b4312f18d..eb8c75741c0c0 100644
--- a/llvm/test/Transforms/LoopVectorize/memdep.ll
+++ b/llvm/test/Transforms/LoopVectorize/memdep.ll
@@ -244,7 +244,7 @@ for.end:
; RIGHTVF-LABEL: @pr34283
; RIGHTVF: <4 x i64>
-; WRONGVF-LABLE: @pr34283
+; WRONGVF-LABEL: @pr34283
; WRONGVF-NOT: <8 x i64>
@a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16
diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
index 430baa1cb4f8c..c426737963c52 100644
--- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
+++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
@@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"
declare i64 @julia_steprange_last_4949()
define void @"japi1_align!_9477"(ptr %arg) {
-; LV-LAVEL: L26.lver.check
+; LV-LABEL: L26.lver.check
; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]])
; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0
; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1
diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
index e6c2a7e629a5d..cea752ad6898d 100644
--- a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
+++ b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
@@ -21,7 +21,7 @@ entry:
define float @f_writeonly(float %val) {
; CHECK-LABEL: @f_writeonly(
-; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
+; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
%res = tail call float @sqrtf(float %val) writeonly
ret float %res
}
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
index bb370a6d1dfeb..7f7790cecb0eb 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
@@ -670,7 +670,7 @@ declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) {
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i1 %slc
- ; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
+ ; CHECK-NEXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
ret void
}
diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test
index c056565f144c5..498febdac0193 100644
--- a/llvm/test/tools/llvm-ar/replace-update.test
+++ b/llvm/test/tools/llvm-ar/replace-update.test
@@ -57,7 +57,7 @@
# MULTIPLE-SYM: symbolnew1
# MULTIPLE-SYM-NEXT: symbol2
-# MULTIPLE-SYM-NEXTs: symbolnew3
+# MULTIPLE-SYM-NEXT: symbolnew3
## Replace newer members with multiple older files:
# RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o
>From 2a37722eb00c2ab55abee53c2f281dc17c173232 Mon Sep 17 00:00:00 2001
From: klensy <klensy at users.noreply.github.com>
Date: Sat, 11 May 2024 17:51:25 +0300
Subject: [PATCH 2/4] and few more
---
llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
index 29621a0477418..1151bde02ef62 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
@@ -4,7 +4,7 @@
---
-# GCN-label: name: vop3
+# GCN-LABEL: name: vop3
# GCN: %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64_dpp %3, %0, %1, %5, 1, 1, 15, 15, 1, implicit $exec
# GCN: %8:vgpr_32 = V_CVT_PK_U8_F32_e64_dpp %3, 4, %0, 2, %2, 2, %1, 1, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec
@@ -37,7 +37,7 @@ body: |
...
---
-# GCN-label: name: vop3_sgpr_src1
+# GCN-LABEL: name: vop3_sgpr_src1
# GCN: %6:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %1, 0, %2, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
# GFX1100: %8:vgpr_32 = V_MED3_F32_e64 0, %7, 0, %2, 0, %1, 0, 0, implicit $mode, implicit $exec
# GFX1150: %8:vgpr_32 = V_MED3_F32_e64_dpp %4, 0, %0, 0, %2, 0, %1, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
@@ -81,7 +81,7 @@ body: |
---
# Regression test for src_modifiers on base u16 opcode
-# GCN-label: name: vop3_u16
+# GCN-LABEL: name: vop3_u16
# GCN: %5:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 0, %1, 0, %3, 0, 0, 1, 15, 15, 1, implicit $exec
# GCN: %7:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 1, %5, 2, %5, 0, 0, 1, 15, 15, 1, implicit $exec
# GCN: %9:vgpr_32 = V_ADD_NC_U16_e64 4, %8, 8, %7, 0, 0, implicit $exec
@@ -205,7 +205,7 @@ body: |
...
# do not combine, dpp arg used twice
-# GCN-label: name: dpp_arg_twice
+# GCN-LABEL: name: dpp_arg_twice
# GCN: %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec
# GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec
# GCN: %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec
@@ -231,7 +231,7 @@ body: |
...
# when the dpp source isn't a src0 operand the operation should be commuted if possible
-# GCN-label: name: dpp_commute_e64
+# GCN-LABEL: name: dpp_commute_e64
# GCN: %4:vgpr_32 = V_MUL_U32_U24_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
# GCN: %7:vgpr_32 = V_FMA_F32_e64_dpp %5, 2, %0, 1, %1, 2, %1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
# GCN: %10:vgpr_32 = V_SUBREV_U32_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
>From ed88501007a3981d7e261f3b4bfe93a1bfd4a702 Mon Sep 17 00:00:00 2001
From: klensy <klensy at users.noreply.github.com>
Date: Sat, 11 May 2024 18:17:50 +0300
Subject: [PATCH 3/4] and few more
---
llvm/test/CodeGen/AArch64/fpimm.ll | 2 +-
llvm/test/CodeGen/ARM/shifter_operand.ll | 1 -
llvm/test/CodeGen/ARM/sxt_rot.ll | 1 -
.../Thumb2/LowOverheadLoops/branch-targets.ll | 6 ++---
.../Mips/mips32r6/valid-mips32r6.txt | 6 ++---
.../Mips/mips64r6/valid-mips64r6.txt | 6 ++---
llvm/test/MC/Mips/macro-rem.s | 2 +-
.../Coroutines/coro-debug-coro-frame.ll | 2 +-
.../AArch64/nontemporal-load-store.ll | 22 +++++++++----------
.../Inputs/binary-formats.canonical.json | 2 +-
10 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll
index b92bb4245c7f3..e2944243338f5 100644
--- a/llvm/test/CodeGen/AArch64/fpimm.ll
+++ b/llvm/test/CodeGen/AArch64/fpimm.ll
@@ -38,7 +38,7 @@ define void @check_double() {
; 64-bit ORR followed by MOVK.
; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844
; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
-; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
+; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
%newval3 = fadd double %val, 0xFCFCFC00FC
store volatile double %newval3, ptr @varf64
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll
index bf2e8aa911c64..00922b1bf2492 100644
--- a/llvm/test/CodeGen/ARM/shifter_operand.ll
+++ b/llvm/test/CodeGen/ARM/shifter_operand.ll
@@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT: orrs r0, r1
; CHECK-THUMB-NEXT: bx lr
entry:
-; CHECk-THUMB: orrs r0, r1
%mul = mul i32 %y, 63767
%or = or i32 %mul, %x
ret i32 %or
diff --git a/llvm/test/CodeGen/ARM/sxt_rot.ll b/llvm/test/CodeGen/ARM/sxt_rot.ll
index e9649c7a7fd9a..775e45201105c 100644
--- a/llvm/test/CodeGen/ARM/sxt_rot.ll
+++ b/llvm/test/CodeGen/ARM/sxt_rot.ll
@@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT: sbfx r0, r0, #8, #8
; CHECK-V7-NEXT: bx lr
-; CHECk-V7: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
index 165e73c2e8827..680d9e02a5c5c 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
@@ -406,7 +406,7 @@ for.cond.cleanup:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_xor_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
@@ -440,7 +440,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_cmp_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
@@ -474,7 +474,7 @@ while.end:
; CHECK-MID: tB %bb.1
; CHECK-MID: bb.1.while.body:
; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1
-; CHECk-MID: tB %bb.2
+; CHECK-MID: tB %bb.2
; CHECK-MID: bb.2.while.end:
define void @check_negated_reordered_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
entry:
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index e1ba009f3c4c8..9708821affae0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -39,7 +39,7 @@
0x04 0x11 0x14 0x9b # CHECK: bal 21104
# The encode/decode functions are not inverses of each other.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
-0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
+0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
@@ -162,13 +162,13 @@
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
-0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
+0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
-0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
+0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 0030e51d6c238..28cd1619e80ad 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -56,7 +56,7 @@
0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
-0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
+0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20
# The encode/decode functions are not inverses of each other in the immediate case.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
@@ -181,13 +181,13 @@
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
-0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
+0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
-0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
+0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
diff --git a/llvm/test/MC/Mips/macro-rem.s b/llvm/test/MC/Mips/macro-rem.s
index 40812949664d6..1f10a5392c07f 100644
--- a/llvm/test/MC/Mips/macro-rem.s
+++ b/llvm/test/MC/Mips/macro-rem.s
@@ -95,7 +95,7 @@
# CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [A,A,0xc0,0x14]
# CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x1a,0x00,0xa6,0x00]
# CHECK-NOTRAP: break 7 # encoding: [0x0d,0x00,0x07,0x00]
-# CHECk-NOTRAP: $tmp2
+# CHECK-NOTRAP: $tmp2
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK-NOTRAP: bne $6, $1, $tmp3 # encoding: [A,A,0xc1,0x14]
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
diff --git a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
index 2978f85be2385..37fb9fea77044 100644
--- a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
+++ b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
@@ -39,7 +39,7 @@
; CHECK-DAG: ![[UNALIGNED_UNKNOWN]] = !DIDerivedType(tag: DW_TAG_member, name: "_6",{{.*}}baseType: ![[UNALIGNED_UNKNOWN_BASE:[0-9]+]], size: 9
; CHECK-DAG: ![[UNALIGNED_UNKNOWN_BASE]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[UNKNOWN_TYPE_BASE]], size: 16,{{.*}} elements: ![[UNALIGNED_UNKNOWN_ELEMENTS:[0-9]+]])
; CHECK-DAG: ![[UNALIGNED_UNKNOWN_ELEMENTS]] = !{![[UNALIGNED_UNKNOWN_SUBRANGE:[0-9]+]]}
-; CHECk-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0)
+; CHECK-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0)
; CHECK-DAG: ![[STRUCT]] = !DIDerivedType(tag: DW_TAG_member, name: "struct_big_structure_7", scope: ![[FRAME_TYPE]], file: ![[FILE]], line: [[PROMISE_VAR_LINE]], baseType: ![[STRUCT_BASE:[0-9]+]]
; CHECK-DAG: ![[STRUCT_BASE]] = !DICompositeType(tag: DW_TAG_structure_type, name: "struct_big_structure"{{.*}}, align: 64, flags: DIFlagArtificial, elements: ![[STRUCT_ELEMENTS:[0-9]+]]
; CHECK-DAG: ![[STRUCT_ELEMENTS]] = !{![[MEM_TYPE:[0-9]+]]}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
index 75f03c7b1a699..c7edf9bdfaf6b 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
@@ -259,7 +259,7 @@ for.cond.cleanup: ; preds = %for.body
define i4 @test_i4_load(ptr %ddst) {
; CHECK-LABEL: define i4 @test_i4_load
; CHECK-NOT: vector.body:
-; CHECk: ret i4 %{{.*}}
+; CHECK: ret i4 %{{.*}}
;
entry:
br label %for.body
@@ -282,7 +282,7 @@ define i8 @test_load_i8(ptr %ddst) {
; CHECK-LABEL: @test_load_i8(
; CHECK: vector.body:
; CHECK: load <4 x i8>, ptr {{.*}}, align 1, !nontemporal !0
-; CHECk: ret i8 %{{.*}}
+; CHECK: ret i8 %{{.*}}
;
entry:
br label %for.body
@@ -305,7 +305,7 @@ define half @test_half_load(ptr %ddst) {
; CHECK-LABEL: @test_half_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x half>, ptr {{.*}}, align 2, !nontemporal !0
-; CHECk: ret half %{{.*}}
+; CHECK: ret half %{{.*}}
;
entry:
br label %for.body
@@ -328,7 +328,7 @@ define i16 @test_i16_load(ptr %ddst) {
; CHECK-LABEL: @test_i16_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i16>, ptr {{.*}}, align 2, !nontemporal !0
-; CHECk: ret i16 %{{.*}}
+; CHECK: ret i16 %{{.*}}
;
entry:
br label %for.body
@@ -351,7 +351,7 @@ define i32 @test_i32_load(ptr %ddst) {
; CHECK-LABEL: @test_i32_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i32>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i32 %{{.*}}
+; CHECK: ret i32 %{{.*}}
;
entry:
br label %for.body
@@ -373,7 +373,7 @@ for.cond.cleanup: ; preds = %for.body
define i33 @test_i33_load(ptr %ddst) {
; CHECK-LABEL: @test_i33_load
; CHECK-NOT: vector.body:
-; CHECk: ret i33 %{{.*}}
+; CHECK: ret i33 %{{.*}}
;
entry:
br label %for.body
@@ -395,7 +395,7 @@ for.cond.cleanup: ; preds = %for.body
define i40 @test_i40_load(ptr %ddst) {
; CHECK-LABEL: @test_i40_load
; CHECK-NOT: vector.body:
-; CHECk: ret i40 %{{.*}}
+; CHECK: ret i40 %{{.*}}
;
entry:
br label %for.body
@@ -418,7 +418,7 @@ define i64 @test_i64_load(ptr %ddst) {
; CHECK-LABEL: @test_i64_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i64>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i64 %{{.*}}
+; CHECK: ret i64 %{{.*}}
;
entry:
br label %for.body
@@ -441,7 +441,7 @@ define double @test_double_load(ptr %ddst) {
; CHECK-LABEL: @test_double_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x double>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret double %{{.*}}
+; CHECK: ret double %{{.*}}
;
entry:
br label %for.body
@@ -464,7 +464,7 @@ define i128 @test_i128_load(ptr %ddst) {
; CHECK-LABEL: @test_i128_load
; CHECK-LABEL: vector.body:
; CHECK: load <4 x i128>, ptr {{.*}}, align 4, !nontemporal !0
-; CHECk: ret i128 %{{.*}}
+; CHECK: ret i128 %{{.*}}
;
entry:
br label %for.body
@@ -486,7 +486,7 @@ for.cond.cleanup: ; preds = %for.body
define i256 @test_256_load(ptr %ddst) {
; CHECK-LABEL: @test_256_load
; CHECK-NOT: vector.body:
-; CHECk: ret i256 %{{.*}}
+; CHECK: ret i256 %{{.*}}
;
entry:
br label %for.body
diff --git a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
index ce13fc2ff6e34..33c517da91b5e 100644
--- a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
+++ b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json
@@ -29,7 +29,7 @@ CHECK-SAME: {"branches":{"count":0,"covered":0,"notcovered":0,"percent":0},
CHECK-SAME: "functions":{"count":1,"covered":1,"percent":100},
CHECK-SAME: "instantiations":{"count":1,"covered":1,"percent":100},
CHECK-SAME: "lines":{"count":1,"covered":1,"percent":100},
-CHECk-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0},
+CHECK-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0},
CHECK-SAME: "regions":{"count":1,"covered":1,"notcovered":0,"percent":100}}}
CHECK-SAME: ],
CHECK-SAME: "type":"llvm.coverage.json.export"
>From c8cc87d1da69af8af5048f83aaed8935ac0bc881 Mon Sep 17 00:00:00 2001
From: klensy <klensy at users.noreply.github.com>
Date: Sat, 11 May 2024 19:03:47 +0300
Subject: [PATCH 4/4] qfew more; something odd
---
llvm/test/Assembler/bfloat.ll | 8 ++++----
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll | 2 +-
.../CodeGen/AArch64/speculation-hardening-sls.ll | 4 ++--
llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 2 +-
llvm/test/CodeGen/NVPTX/idioms.ll | 10 +++++-----
llvm/test/CodeGen/SPARC/inlineasm.ll | 2 +-
.../MIR/InstrRef/single-assign-propagation.mir | 6 +++---
llvm/test/MC/RISCV/zicfiss-valid.s | 12 ++++++------
.../SampleProfile/pseudo-probe-selectionDAG.ll | 4 ++--
llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s | 2 +-
polly/test/CodeGen/alias_metadata_too_many_arrays.ll | 2 +-
11 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/llvm/test/Assembler/bfloat.ll b/llvm/test/Assembler/bfloat.ll
index 3a3b4c2b277db..6f935c5dac154 100644
--- a/llvm/test/Assembler/bfloat.ll
+++ b/llvm/test/Assembler/bfloat.ll
@@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
ret float %tmp
}
-; ASSEM-DISASS-LABEL @snan_bfloat
+; ASSEM-DISASS-LABEL: @snan_bfloat
define bfloat @snan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F81
ret bfloat 0xR7F81
}
-; ASSEM-DISASS-LABEL @qnan_bfloat
+; ASSEM-DISASS-LABEL: @qnan_bfloat
define bfloat @qnan_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7FC0
ret bfloat 0xR7FC0
}
-; ASSEM-DISASS-LABEL @pos_inf_bfloat
+; ASSEM-DISASS-LABEL: @pos_inf_bfloat
define bfloat @pos_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xR7F80
ret bfloat 0xR7F80
}
-; ASSEM-DISASS-LABEL @neg_inf_bfloat
+; ASSEM-DISASS-LABEL: @neg_inf_bfloat
define bfloat @neg_inf_bfloat() {
; ASSEM-DISASS: ret bfloat 0xRFF80
ret bfloat 0xRFF80
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index e9556b9d5cbee..e93fcec822846 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
define void @no_op() nounwind {
-; CHECK-LABEL .def $ientry_thunk$cdecl$v$v;
+; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v;
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill
diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
index f380b2d05d863..fe08fa5642574 100644
--- a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
@@ -192,7 +192,7 @@ entry:
; CHECK: .Lfunc_end
}
-; HARDEN-label: __llvm_slsblr_thunk_x0:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
; HARDEN: mov x16, x0
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
@@ -208,7 +208,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19
; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19, at function
-; HARDEN-label: __llvm_slsblr_thunk_x19:
+; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
; HARDEN: mov x16, x19
; HARDEN: br x16
; ISBDSB-NEXT: dsb sy
diff --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
index f25d73a12246f..1f60f120dc86a 100644
--- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
@@ -248,7 +248,7 @@ entry:
; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}}
; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function
-; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
+; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
; HARDEN: bx r5
; ISBDSB-NEXT: dsb sy
; ISBDSB-NEXT: isb
diff --git a/llvm/test/CodeGen/NVPTX/idioms.ll b/llvm/test/CodeGen/NVPTX/idioms.ll
index e8fe47c303f92..0669d2a3717cb 100644
--- a/llvm/test/CodeGen/NVPTX/idioms.ll
+++ b/llvm/test/CodeGen/NVPTX/idioms.ll
@@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) {
%high = trunc i32 %high32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
@@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) {
%low = trunc i32 %in to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0];
; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
%s1 = insertvalue %struct.S16 poison, i16 %low, 0
%s = insertvalue %struct.S16 %s1, i16 %high, 1
ret %struct.S16 %s
@@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) {
%high = trunc i64 %high64 to i32
; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0];
; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]];
-; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
+; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]];
%s1 = insertvalue %struct.S32 poison, i32 %low, 0
%s = insertvalue %struct.S32 %s1, i32 %high, 1
ret %struct.S32 %s
@@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){
%h = trunc i32 %h32 to i16
; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0];
; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16;
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
-; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]];
+; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]];
%s0 = insertvalue %struct.S16 poison, i16 %l, 0
%s1 = insertvalue %struct.S16 %s0, i16 %h, 1
ret %struct.S16 %s1
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll
index 9817d7c6971f5..786e9f3eb1e13 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -144,7 +144,7 @@ entry:
ret void
}
-; CHECK-label:test_twinword
+; CHECK-LABEL:test_twinword
; CHECK: rd %asr5, %i1
; CHECK: srlx %i1, 32, %i0
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
index 8f43a55b34001..3649b136d3900 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
@@ -55,11 +55,11 @@
## to bb.3, but not into bb.4 because of the intervening out-of-scope block.
## Disabled actual testing of this because it's just for comparison purposes.
#
-# varloc-label: bb.1:
+# varloc-LABEL: bb.1:
# varloc: DBG_VALUE
-# varloc-label: bb.2:
+# varloc-LABEL: bb.2:
## No location here because it's out-of-scope.
-# varloc-label: bb.3:
+# varloc-LABEL: bb.3:
# varloc: DBG_VALUE
#
## Common tail for 'test2' -- this is checking that the assignment of undef or
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index fd69d37d7cfa0..3280bd2ae3797 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -44,14 +44,14 @@ sspush x1
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush ra
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-ASM-AND-OBJ: sspush t0
+# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush x5
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0xce]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-ASM-AND-OBJ: sspush t0
+# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush t0
# CHECK-ASM-AND-OBJ: ssrdp ra
diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
index 5d01e78221e38..3bc18c7cdd7bf 100644
--- a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
+++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
@@ -10,7 +10,7 @@ entry:
if.end: ; preds = %entry
;; Check pseudo probes are next to each other at the beginning of this block.
-; IR-label: if.end
+; IR-LABEL: if.end
; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)
; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1)
call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)
@@ -19,7 +19,7 @@ if.end: ; preds = %entry
%2 = and i16 %1, 16
%3 = icmp eq i16 %2, 0
;; Check the load-and-cmp sequence is fold into a test instruction.
-; MIR-label: bb.1.if.end
+; MIR-LABEL: bb.1.if.end
; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF
; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 16
; MIR: JCC_1
diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
index 771bce5023933..37271fb902b4d 100644
--- a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
@@ -5,6 +5,6 @@
strd:
strd r0, r1, [r2, +r3]
-@ CHECK-LABEL strd
+@ CHECK-LABEL: strd
@ CHECK: e18200f3 strd r0, r1, [r2, r3]
diff --git a/polly/test/CodeGen/alias_metadata_too_many_arrays.ll b/polly/test/CodeGen/alias_metadata_too_many_arrays.ll
index 7c5ca012a3783..b9633defa0661 100644
--- a/polly/test/CodeGen/alias_metadata_too_many_arrays.ll
+++ b/polly/test/CodeGen/alias_metadata_too_many_arrays.ll
@@ -16,7 +16,7 @@
; }
; }
;
-; CHECK-LABEL @manyarrays
+; CHECK-LABEL: @manyarrays
; CHECK: load{{.*}}!alias.scope
; CHECK: store{{.*}}!alias.scope
; CHECK: load{{.*}}!alias.scope
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