[llvm] [DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (PR #92096)

[Simon Pilgrim via llvm-commits]

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@@ -4560,8 +4560,15 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
     // SRA X, C -> adds C sign bits.
     if (const APInt *ShAmt =
-            getValidMinimumShiftAmountConstant(Op, DemandedElts))
+            getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
       Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
+    } else {
+      KnownBits KnownAmt =
+          computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+      if (KnownAmt.isConstant() && KnownAmt.getConstant().ult(VTBits))
+        Tmp = std::min<uint64_t>(Tmp + KnownAmt.getConstant().getZExtValue(),
+                                 VTBits);
+    }
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RKSimon wrote:

Yes, its mainly just a sanity/overflow check (somebody always comes along with a i1024 fuzz test or something eventually that makes getZExtValue() assert or cause weird getLimitedValue() behaviour).

Using getMaxValue() was mainly to try and keep closer to the behaviour of getValidMinimumShiftAmountConstant which doesn't accept out of bounds shift amounts.

https://github.com/llvm/llvm-project/pull/92096