[llvm] 4e0f8a4 - [AMDGPU] Fix EXPENSIVE_CHECKS failure in #89612

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-05-23T12:22:25+01:00
New Revision: 4e0f8a4919b1920ed715ca19314e6b3e06a70763

URL: https://github.com/llvm/llvm-project/commit/4e0f8a4919b1920ed715ca19314e6b3e06a70763
DIFF: https://github.com/llvm/llvm-project/commit/4e0f8a4919b1920ed715ca19314e6b3e06a70763.diff

LOG: [AMDGPU] Fix EXPENSIVE_CHECKS failure in #89612

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 99109b23a1591..04d9bb5cb18a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2089,7 +2089,7 @@ bool AMDGPUInstructionSelector::selectPOPSExitingWaveID(
   // intrinsic is IntrReadMem/IntrWriteMem but the instruction is not marked
   // mayLoad/mayStore and tablegen complains about the mismatch.
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), Dst)
-                 .addDef(AMDGPU::SRC_POPS_EXITING_WAVE_ID);
+                 .addReg(AMDGPU::SRC_POPS_EXITING_WAVE_ID);
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 }