[llvm] [AMDGPU] Introduce address sanitizer instrumentation for LDS lowered by amdgpu-sw-lower-lds pass (PR #89208)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 04:16:38 PDT 2024
================
@@ -0,0 +1,249 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32, i32 }
+
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol !0
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 1, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 4, i32 8 } }, no_sanitize_address
+
+; Function Attrs: sanitize_address
+;.
+; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
+; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %0 { %1 { i32 0, i32 8, i32 32, i32 8, i32 24 }, %1 { i32 32, i32 1, i32 32, i32 33, i32 31 }, %1 { i32 64, i32 4, i32 32, i32 68, i32 28 } }, no_sanitize_address, align 1
+; CHECK: @llvm.used = appending addrspace(1) global [1 x ptr] [ptr @asan.module_ctor], section "llvm.metadata"
+; CHECK: @___asan_globals_registered = common hidden addrspace(1) global i64 0
+; CHECK: @__start_asan_globals = extern_weak hidden addrspace(1) global i64
+; CHECK: @__stop_asan_globals = extern_weak hidden addrspace(1) global i64
+; CHECK: @llvm.global_ctors = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_ctor, ptr @asan.module_ctor }]
+;.
+define amdgpu_kernel void @k0() #0 {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[WID:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB32:.*]]
+; CHECK: [[MALLOC]]:
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
+; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress(i32 0)
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP9]], i64 [[TMP11]])
+; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr addrspace(1)
+; CHECK-NEXT: store ptr addrspace(1) [[TMP13]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 3), align 4
+; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 [[TMP15]]
+; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr addrspace(1) [[TMP16]] to i64
+; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 4), align 4
+; CHECK-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP17]], i64 [[TMP19]])
+; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 4
+; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 [[TMP21]]
+; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr addrspace(1) [[TMP22]] to i64
+; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 4), align 4
+; CHECK-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP23]], i64 [[TMP25]])
+; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 4
+; CHECK-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 [[TMP27]]
+; CHECK-NEXT: [[TMP29:%.*]] = ptrtoint ptr addrspace(1) [[TMP28]] to i64
+; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 4), align 4
+; CHECK-NEXT: [[TMP31:%.*]] = zext i32 [[TMP30]] to i64
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP29]], i64 [[TMP31]])
+; CHECK-NEXT: br label %[[BB32]]
+; CHECK: [[BB32]]:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, %[[WID]] ], [ true, %[[MALLOC]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP33]]
+; CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP35]]
+; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr addrspace(3) [[TMP34]] to i32
+; CHECK-NEXT: [[TMP38:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP38]], i32 [[TMP37]]
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(1) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[TMP46]] to i8
+; CHECK-NEXT: [[TMP48:%.*]] = icmp sge i8 [[TMP47]], [[TMP44]]
+; CHECK-NEXT: [[TMP49:%.*]] = and i1 [[TMP45]], [[TMP48]]
+; CHECK-NEXT: [[TMP50:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP49]])
+; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[TMP50]], 0
+; CHECK-NEXT: br i1 [[TMP51]], label %[[ASAN_REPORT:.*]], label %[[BB54:.*]], !prof [[PROF1:![0-9]+]]
+; CHECK: [[ASAN_REPORT]]:
+; CHECK-NEXT: br i1 [[TMP49]], label %[[BB52:.*]], label %[[BB53:.*]]
+; CHECK: [[BB52]]:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP40]]) #[[ATTR7:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label %[[BB53]]
+; CHECK: [[BB53]]:
+; CHECK-NEXT: br label %[[BB54]]
+; CHECK: [[BB54]]:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP34]], align 4
+; CHECK-NEXT: [[TMP55:%.*]] = ptrtoint ptr addrspace(3) [[TMP36]] to i64
+; CHECK-NEXT: [[TMP56:%.*]] = add i64 [[TMP55]], 3
+; CHECK-NEXT: [[TMP57:%.*]] = inttoptr i64 [[TMP56]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr addrspace(3) [[TMP36]] to i32
+; CHECK-NEXT: [[TMP59:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP59]], i32 [[TMP58]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr addrspace(1) [[TMP60]] to i64
+; CHECK-NEXT: [[TMP62:%.*]] = lshr i64 [[TMP61]], 3
+; CHECK-NEXT: [[TMP63:%.*]] = add i64 [[TMP62]], 2147450880
+; CHECK-NEXT: [[TMP64:%.*]] = inttoptr i64 [[TMP63]] to ptr
+; CHECK-NEXT: [[TMP65:%.*]] = load i8, ptr [[TMP64]], align 1
+; CHECK-NEXT: [[TMP66:%.*]] = icmp ne i8 [[TMP65]], 0
+; CHECK-NEXT: [[TMP67:%.*]] = and i64 [[TMP61]], 7
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP65]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP66]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label %[[ASAN_REPORT1:.*]], label %[[BB75:.*]], !prof [[PROF1]]
+; CHECK: [[ASAN_REPORT1]]:
+; CHECK-NEXT: br i1 [[TMP70]], label %[[BB73:.*]], label %[[BB74:.*]]
+; CHECK: [[BB73]]:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP61]], i64 4) #[[ATTR7]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label %[[BB74]]
+; CHECK: [[BB74]]:
+; CHECK-NEXT: br label %[[BB75]]
+; CHECK: [[BB75]]:
+; CHECK-NEXT: [[TMP76:%.*]] = ptrtoint ptr addrspace(3) [[TMP57]] to i32
+; CHECK-NEXT: [[TMP77:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP77]], i32 [[TMP76]]
+; CHECK-NEXT: [[TMP79:%.*]] = ptrtoint ptr addrspace(1) [[TMP78]] to i64
+; CHECK-NEXT: [[TMP80:%.*]] = lshr i64 [[TMP79]], 3
+; CHECK-NEXT: [[TMP81:%.*]] = add i64 [[TMP80]], 2147450880
+; CHECK-NEXT: [[TMP82:%.*]] = inttoptr i64 [[TMP81]] to ptr
+; CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[TMP82]], align 1
+; CHECK-NEXT: [[TMP84:%.*]] = icmp ne i8 [[TMP83]], 0
+; CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP79]], 7
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP83]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP84]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label %[[ASAN_REPORT2:.*]], label %[[BB93:.*]], !prof [[PROF1]]
+; CHECK: [[ASAN_REPORT2]]:
+; CHECK-NEXT: br i1 [[TMP88]], label %[[BB91:.*]], label %[[BB92:.*]]
+; CHECK: [[BB91]]:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP79]], i64 4) #[[ATTR7]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label %[[BB92]]
+; CHECK: [[BB92]]:
+; CHECK-NEXT: br label %[[BB93]]
+; CHECK: [[BB93]]:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP36]], align 2
+; CHECK-NEXT: br label %[[CONDFREE:.*]]
+; CHECK: [[CONDFREE]]:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label %[[FREE:.*]], label %[[END:.*]]
+; CHECK: [[FREE]]:
+; CHECK-NEXT: [[TMP94:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP95:%.*]] = call ptr @llvm.returnaddress(i32 0)
+; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr [[TMP95]] to i64
+; CHECK-NEXT: [[TMP97:%.*]] = ptrtoint ptr addrspace(1) [[TMP94]] to i64
+; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP97]], i64 [[TMP96]])
+; CHECK-NEXT: br label %[[END]]
+; CHECK: [[END]]:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %14
+
----------------
arsenm wrote:
There's a lot going on in these test functions. Can you use simple tests that show single operations? Also need to test an arbitrary call user of a pointer
https://github.com/llvm/llvm-project/pull/89208
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