[llvm] [SPIR-V] Inline assembly support (PR #93164)
Vyacheslav Levytskyy via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 03:49:10 PDT 2024
https://github.com/VyacheslavLevytskyy updated https://github.com/llvm/llvm-project/pull/93164
>From 3222c7acd8c67f6c5aed1f9cb85732f26674fcb5 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Tue, 21 May 2024 02:22:37 -0700
Subject: [PATCH 1/7] general IR translator support of inline asm
---
llvm/lib/Target/SPIRV/CMakeLists.txt | 1 +
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 9 ++++
llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 9 ++++
.../Target/SPIRV/SPIRVInlineAsmLowering.cpp | 46 ++++++++++++++++
.../lib/Target/SPIRV/SPIRVInlineAsmLowering.h | 33 ++++++++++++
llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td | 6 ++-
llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 1 +
llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 5 ++
.../SPV_INTEL_inline_assembly/inline_asm.ll | 52 +++++++++++++++++++
10 files changed, 161 insertions(+), 3 deletions(-)
create mode 100644 llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.cpp
create mode 100644 llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.h
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
diff --git a/llvm/lib/Target/SPIRV/CMakeLists.txt b/llvm/lib/Target/SPIRV/CMakeLists.txt
index 7001ac382f41c..fe09d5903045c 100644
--- a/llvm/lib/Target/SPIRV/CMakeLists.txt
+++ b/llvm/lib/Target/SPIRV/CMakeLists.txt
@@ -17,6 +17,7 @@ add_llvm_target(SPIRVCodeGen
SPIRVAsmPrinter.cpp
SPIRVBuiltins.cpp
SPIRVCallLowering.cpp
+ SPIRVInlineAsmLowering.cpp
SPIRVCommandLine.cpp
SPIRVDuplicatesTracker.cpp
SPIRVEmitIntrinsics.cpp
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 96b4a570a26b1..519c6b66aba98 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -82,6 +82,15 @@ bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
return false;
}
+std::pair<unsigned, const TargetRegisterClass *>
+SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+ StringRef Constraint,
+ MVT VT) const {
+ if (Constraint.starts_with("{"))
+ return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
+ return std::make_pair(0u, &SPIRV::ID64RegClass);
+}
+
// Insert a bitcast before the instruction to keep SPIR-V code valid
// when there is a type mismatch between results and operand types.
static void validatePtrTypes(const SPIRVSubtarget &STI,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 8c1de7d97d1a3..6fc200abf4627 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -55,6 +55,15 @@ class SPIRVTargetLowering : public TargetLowering {
MachineFunction &MF,
unsigned Intrinsic) const override;
+ std::pair<unsigned, const TargetRegisterClass *>
+ getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+ StringRef Constraint, MVT VT) const override;
+ unsigned
+ getNumRegisters(LLVMContext &Context, EVT VT,
+ std::optional<MVT> RegisterVT = std::nullopt) const override {
+ return 1;
+ }
+
// Call the default implementation and finalize target lowering by inserting
// extra instructions required to preserve validity of SPIR-V code imposed by
// the standard.
diff --git a/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.cpp
new file mode 100644
index 0000000000000..8bd4fb6bf8b11
--- /dev/null
+++ b/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.cpp
@@ -0,0 +1,46 @@
+//===--- SPIRVInlineAsmLowering.cpp - Inline Asm lowering -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the lowering of LLVM inline asm calls to machine code
+// calls for GlobalISel.
+//
+//===----------------------------------------------------------------------===//
+
+#include "SPIRVInlineAsmLowering.h"
+#include "SPIRVSubtarget.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/IntrinsicsSPIRV.h"
+
+using namespace llvm;
+
+SPIRVInlineAsmLowering::SPIRVInlineAsmLowering(const SPIRVTargetLowering &TLI)
+ : InlineAsmLowering(&TLI) {}
+
+bool SPIRVInlineAsmLowering::lowerAsmOperandForConstraint(
+ Value *Val, StringRef Constraint, std::vector<MachineOperand> &Ops,
+ MachineIRBuilder &MIRBuilder) const {
+ Value *ValOp = nullptr;
+ if (isa<ConstantInt>(Val)) {
+ ValOp = Val;
+ } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Val)) {
+ Ops.push_back(MachineOperand::CreateFPImm(CFP));
+ return true;
+ } else if (auto *II = dyn_cast<IntrinsicInst>(Val)) {
+ if (II->getIntrinsicID() == Intrinsic::spv_track_constant) {
+ if (isa<ConstantInt>(II->getOperand(0))) {
+ ValOp = II->getOperand(0);
+ } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(II->getOperand(0))) {
+ Ops.push_back(MachineOperand::CreateFPImm(CFP));
+ return true;
+ }
+ }
+ }
+ return ValOp ? InlineAsmLowering::lowerAsmOperandForConstraint(
+ ValOp, Constraint, Ops, MIRBuilder)
+ : false;
+}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.h b/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.h
new file mode 100644
index 0000000000000..72291855a18c4
--- /dev/null
+++ b/llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.h
@@ -0,0 +1,33 @@
+//===--- SPIRVInlineAsmLowering.h - Inline Asm lowering ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes how to lower LLVM inline asm calls to machine
+// code calls for GlobalISel.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVINLINEASMLOWERING_H
+#define LLVM_LIB_TARGET_SPIRV_SPIRVINLINEASMLOWERING_H
+
+#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
+
+namespace llvm {
+
+class SPIRVTargetLowering;
+
+class SPIRVInlineAsmLowering : public InlineAsmLowering {
+public:
+ SPIRVInlineAsmLowering(const SPIRVTargetLowering &TLI);
+ bool
+ lowerAsmOperandForConstraint(Value *Val, StringRef Constraint,
+ std::vector<MachineOperand> &Ops,
+ MachineIRBuilder &MIRBuilder) const override;
+};
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_SPIRV_SPIRVINLINEASMLOWERING_H
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
index dea2ef402d3d9..7f7f0f36ae5d3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
@@ -10,4 +10,4 @@
// as InstructionSelector RegClass checking code relies on them
def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
-def IDRegBank : RegisterBank<"IDBank", [ID, fID, pID32, pID64, vID, vfID, vpID32, vpID64]>;
+def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, pID32, pID64, vID, vfID, vpID32, vpID64]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
index 9231d22e8d836..70bbe1da525e6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
@@ -29,6 +29,7 @@ let Namespace = "SPIRV" in {
// Class for non-type registers
def ID0 : Register<"ID0">;
+ def ID640 : Register<"ID640">;
def fID0 : Register<"fID0">;
def pID320 : Register<"pID320">;
def pID640 : Register<"pID640">;
@@ -38,6 +39,7 @@ let Namespace = "SPIRV" in {
def vpID640 : Register<"vpID640">;
def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
+ def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>;
@@ -48,9 +50,9 @@ let Namespace = "SPIRV" in {
def ANYID : RegisterClass<
"SPIRV",
- [i32, f32, p32, p64, v2i32, v2f32, v2p32, v2p64],
+ [i32, i64, f32, p32, p64, v2i32, v2f32, v2p32, v2p64],
32,
- (add ID0, fID0, pID320, pID640, vID0, vfID0, vpID320, vpID640)>;
+ (add ID0, ID640, fID0, pID320, pID640, vID0, vfID0, vpID320, vpID640)>;
// A few instructions like OpName can take ids from both type and non-type
// instructions, so we need a super-class to allow for both to count as valid
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
index 7aa0c566c75f3..27472923ee08c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
@@ -82,6 +82,7 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU,
GR = std::make_unique<SPIRVGlobalRegistry>(PointerSize);
CallLoweringInfo = std::make_unique<SPIRVCallLowering>(TLInfo, GR.get());
+ InlineAsmInfo = std::make_unique<SPIRVInlineAsmLowering>(TLInfo);
Legalizer = std::make_unique<SPIRVLegalizerInfo>(*this);
RegBankInfo = std::make_unique<SPIRVRegisterBankInfo>();
InstSelector.reset(
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
index 3e4044084266c..32fbcf578827e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
@@ -15,6 +15,7 @@
#include "SPIRVCallLowering.h"
#include "SPIRVFrameLowering.h"
+#include "SPIRVInlineAsmLowering.h"
#include "SPIRVISelLowering.h"
#include "SPIRVInstrInfo.h"
#include "llvm/ADT/SmallSet.h"
@@ -54,6 +55,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo {
std::unique_ptr<RegisterBankInfo> RegBankInfo;
std::unique_ptr<LegalizerInfo> Legalizer;
std::unique_ptr<InstructionSelector> InstSelector;
+ std::unique_ptr<InlineAsmLowering> InlineAsmInfo;
// TODO: Initialise the available extensions, extended instruction sets
// based on the environment settings.
@@ -108,6 +110,9 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo {
InstructionSelector *getInstructionSelector() const override {
return InstSelector.get();
}
+ const InlineAsmLowering *getInlineAsmLowering() const override {
+ return InlineAsmInfo.get();
+ }
const SPIRVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const SPIRVFrameLowering *getFrameLowering() const override {
return &FrameLowering;
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
new file mode 100644
index 0000000000000..7d1429f7ef6ee
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -0,0 +1,52 @@
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - -filetype=obj | spirv-val %}
+
+; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; CHECK-ERROR: LLVM ERROR: requires the following SPIR-V extension: SPV_INTEL_inline_assembly
+
+; CHECK: Capability AsmINTEL
+; CHECK: Extension "SPV_INTEL_inline_assembly"
+; CHECK: Decorate SideEffectsINTEL
+; CHECK: AsmTargetINTEL "spir64-unknown-unknown"
+; CHECK: AsmINTEL
+; CHECK: OpFunction
+; CHECK: AsmCallINTEL
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) {
+ %i1 = load i32, ptr addrspace(1) %_arg_int
+ %i2 = load i8, ptr addrspace(1) %_arg_int
+ %f1 = load float, ptr addrspace(1) %_arg_float
+ %h1 = load half, ptr addrspace(1) %_arg_half
+; ; inline asm: complex result
+; call { i64, half } asm sideeffect "structcmd_nop", "=r,=r"()
+; %r_struct = call { i64, half } asm sideeffect "structcmd $0 $0 $1 $1", "=r,=r,0,1"(i64 123, half %h1)
+;; %r_struct1 = extractvalue { i64, half } %r_struct, 0
+;; %r_struct2 = extractvalue { i64, half } %r_struct, 1
+;; store half %r_struct2, ptr addrspace(1) %_arg_half
+ ; inline asm
+ call void asm sideeffect "", ""()
+ call void asm sideeffect "undefined\0A", ""()
+ call void asm sideeffect "", "~{cc},~{memory}"()
+ %res_i0 = call i32 asm "clobber_out $0", "=&r"()
+ store i32 %res_i0, ptr addrspace(1) %_arg_int
+ ; inline asm: integer
+ %res_i1 = call i32 asm sideeffect "icmd $0 $1", "=r,r"(i32 %i1)
+ store i32 %res_i1, ptr addrspace(1) %_arg_int
+ ; inline asm: float
+ %res_f1 = call float asm sideeffect "fcmd $0 $1", "=r,r"(float %f1)
+ store float %res_f1, ptr addrspace(1) %_arg_float
+ ; inline asm: mixed floats
+ %res_f2 = call half asm sideeffect "fcmdext $0 $1 $2", "=r,r,r"(float 2.0, float %f1)
+ store float %res_f1, ptr addrspace(1) %_arg_half
+ ; inline asm: mixed operands of different types
+ call i8 asm sideeffect "cmdext $0 $3 $1 $2", "=r,r,r,r"(float %f1, i32 123, i8 %i2)
+ ; inline asm: mixed integers
+ %res_i2 = call i64 asm sideeffect "icmdext $0 $3 $1 $2", "=r,r,r,r"(i64 %_lng, i32 %i1, i8 %i2)
+ store i64 %res_i2, ptr addrspace(1) %_arg_int
+ ; inline asm: constant arguments
+ call void asm sideeffect "constcmd $0 $1", "i,i"(i32 123, double 42.0)
+ ret void
+}
>From 3441dc5a097962d79c20b169e2eba08aecbf11a0 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Wed, 22 May 2024 04:02:16 -0700
Subject: [PATCH 2/7] translate inline asm
---
llvm/docs/SPIRVUsage.rst | 2 +
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 1 +
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 2 +
llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 37 +++++
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 15 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 14 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h | 1 +
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 9 ++
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 3 +-
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp | 9 +-
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 137 +++++++++++++++++-
llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 1 +
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 4 +
.../SPV_INTEL_inline_assembly/inline_asm.ll | 6 +-
14 files changed, 224 insertions(+), 17 deletions(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index d27177a4541a4..0dfbffd6274e5 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -143,6 +143,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Adds instructions to convert between single-precision 32-bit floating-point values and 16-bit bfloat16 values.
* - ``SPV_INTEL_function_pointers``
- Allows translation of function pointers.
+ * - ``SPV_INTEL_inline_assembly``
+ - Allows to use inline assembly.
* - ``SPV_INTEL_optnone``
- Adds OptNoneINTEL value for Function Control mask that indicates a request to not optimize the function.
* - ``SPV_INTEL_subgroups``
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index cc84decc43407..78997a8312b00 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -36,6 +36,7 @@ let TargetPrefix = "spv" in {
def int_spv_alloca : Intrinsic<[llvm_any_ty], []>;
def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty]>;
def int_spv_undef : Intrinsic<[llvm_i32_ty], []>;
+ def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty]>;
// Expect, Assume Intrinsics
def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 752d71eddd99a..7f531542544ab 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -47,6 +47,8 @@ static const std::map<std::string, SPIRV::Extension::Extension>
SPIRV::Extension::Extension::SPV_KHR_bit_instructions},
{"SPV_KHR_linkonce_odr",
SPIRV::Extension::Extension::SPV_KHR_linkonce_odr},
+ {"SPV_INTEL_inline_assembly",
+ SPIRV::Extension::Extension::SPV_INTEL_inline_assembly},
{"SPV_INTEL_bfloat16_conversion",
SPIRV::Extension::Extension::SPV_INTEL_bfloat16_conversion},
{"SPV_KHR_subgroup_rotate",
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index a1a08c5c699b6..09750667d3176 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -140,6 +140,7 @@ class SPIRVEmitIntrinsics
Instruction *visitAllocaInst(AllocaInst &I);
Instruction *visitAtomicCmpXchgInst(AtomicCmpXchgInst &I);
Instruction *visitUnreachableInst(UnreachableInst &I);
+ Instruction *visitCallInst(CallInst &I);
StringRef getPassName() const override { return "SPIRV emit intrinsics"; }
@@ -629,6 +630,42 @@ void SPIRVEmitIntrinsics::preprocessCompositeConstants(IRBuilder<> &B) {
}
}
+/*
+ Constant *IATyVal = UndefValue::get(IA->getFunctionType());
+ MetadataAsValue *IAtyArg = MetadataAsValue::get(
+ Ctx, MDNode::get(Ctx, ValueAsMetadata::getConstant(IATyVal)));
+// MetadataAsValue *IAtyArg = MetadataAsValue::get(Ctx, ValueAsMetadata::get(&Call));
+ MetadataAsValue *IAStr =
+ MetadataAsValue::get(Ctx, MDString::get(Ctx, IA->getAsmString()));
+ MetadataAsValue *IAConstr =
+ MetadataAsValue::get(Ctx, MDString::get(Ctx, IA->getConstraintString()));
+// SmallVector<Value *> Args = {UndefValue::get(IntegerType::getInt8Ty(Ctx))};//, IAStr, IAStr, IAConstr};
+ SmallVector<Value *> Args = {IAtyArg};//, IAStr, IAStr, IAConstr};
+ IRBuilder<> B(Call.getParent());
+ B.SetInsertPoint(&Call);
+// B.CreateIntrinsic(Intrinsic::spv_inline_asm, {IntegerType::getInt8Ty(Ctx)}, {Args});
+// works with def int_spv_inline_asm : Intrinsic<[], [llvm_any_ty]>; --> B.CreateIntrinsic(Intrinsic::spv_inline_asm, {IAtyArg->getType}, {Args});
+*/
+Instruction *SPIRVEmitIntrinsics::visitCallInst(CallInst &Call) {
+ if (!Call.isInlineAsm())
+ return &Call;
+
+ const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
+ LLVMContext &Ctx = F->getContext();
+
+ Constant *IATyVal = UndefValue::get(IA->getFunctionType());
+ ArrayRef<Metadata *> MDs = {ValueAsMetadata::getConstant(IATyVal),
+ MDString::get(Ctx, IA->getAsmString()),
+ MDString::get(Ctx, IA->getConstraintString())};
+ SmallVector<Value *> Args = {
+ MetadataAsValue::get(Ctx, MDNode::get(Ctx, MDs))};
+
+ IRBuilder<> B(Call.getParent());
+ B.SetInsertPoint(&Call);
+ B.CreateIntrinsic(Intrinsic::spv_inline_asm, {}, {Args});
+ return &Call;
+}
+
Instruction *SPIRVEmitIntrinsics::visitSwitchInst(SwitchInst &I) {
BasicBlock *ParentBB = I.getParent();
IRBuilder<> B(ParentBB);
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 519c6b66aba98..9a95cd8239234 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -86,9 +86,20 @@ std::pair<unsigned, const TargetRegisterClass *>
SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint,
MVT VT) const {
+ const TargetRegisterClass *RC = nullptr;
if (Constraint.starts_with("{"))
- return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
- return std::make_pair(0u, &SPIRV::ID64RegClass);
+ return std::make_pair(0u, RC);
+
+ if (VT.isFloatingPoint())
+ RC = VT.isVector() ? &SPIRV::vfIDRegClass : &SPIRV::fIDRegClass;
+ else if (VT.isInteger())
+ RC = VT.isVector() ? &SPIRV::vIDRegClass
+ : (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
+ : &SPIRV::IDRegClass);
+ else
+ RC = &SPIRV::IDRegClass;
+
+ return std::make_pair(0u, RC);
}
// Insert a bitcast before the instruction to keep SPIR-V code valid
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index af98f2f880459..c69d3fe1eb57b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -47,6 +47,16 @@ bool SPIRVInstrInfo::isConstantInstr(const MachineInstr &MI) const {
}
}
+bool SPIRVInstrInfo::isInlineAsmDefInstr(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
+ case SPIRV::OpAsmTargetINTEL:
+ case SPIRV::OpAsmINTEL:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool SPIRVInstrInfo::isTypeDeclInstr(const MachineInstr &MI) const {
auto &MRI = MI.getMF()->getRegInfo();
if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) {
@@ -246,8 +256,8 @@ void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
bool SPIRVInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
- if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_fID ||
- MI.getOpcode() == SPIRV::GET_pID32 ||
+ if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_ID64 ||
+ MI.getOpcode() == SPIRV::GET_fID || MI.getOpcode() == SPIRV::GET_pID32 ||
MI.getOpcode() == SPIRV::GET_pID64 || MI.getOpcode() == SPIRV::GET_vfID ||
MI.getOpcode() == SPIRV::GET_vID || MI.getOpcode() == SPIRV::GET_vpID32 ||
MI.getOpcode() == SPIRV::GET_vpID64) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index 4f2781c9404b8..95f3874913572 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -30,6 +30,7 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
const SPIRVRegisterInfo &getRegisterInfo() const { return RI; }
bool isHeaderInstr(const MachineInstr &MI) const;
bool isConstantInstr(const MachineInstr &MI) const;
+ bool isInlineAsmDefInstr(const MachineInstr &MI) const;
bool isTypeDeclInstr(const MachineInstr &MI) const;
bool isDecorationInstr(const MachineInstr &MI) const;
bool canUseFastMathFlags(const MachineInstr &MI) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index a6bedab6d4ee5..f420e46623e32 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -18,6 +18,7 @@ let isCodeGenOnly=1 in {
def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
+ def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
def GET_pID64: Pseudo<(outs pID64:$dst_id), (ins ANYID:$src)>;
@@ -854,3 +855,11 @@ def OpGroupLogicalOrKHR: Op<6407, (outs ID:$res), (ins TYPE:$type, ID:$scope, i3
"$res = OpGroupLogicalOrKHR $type $scope $groupOp $value">;
def OpGroupLogicalXorKHR: Op<6408, (outs ID:$res), (ins TYPE:$type, ID:$scope, i32imm:$groupOp, ID:$value),
"$res = OpGroupLogicalXorKHR $type $scope $groupOp $value">;
+
+// Inline Assembly Instructions
+def OpAsmTargetINTEL: Op<5609, (outs ID:$res), (ins StringImm:$str), "$res = OpAsmTargetINTEL $str">;
+def OpAsmINTEL: Op<5610, (outs ID:$res), (ins TYPE:$type, TYPE:$asm_type, ID:$target,
+ StringImm:$asm, StringImm:$constraints),
+ "$res = OpAsmINTEL $type $asm_type $target $asm $constraints">;
+def OpAsmCallINTEL: Op<5611, (outs ID:$res), (ins TYPE:$type, ID:$asm, variable_ops),
+ "$res = OpAsmCallINTEL $type $asm">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index cbe7c5ca30570..c8103ee01e3ca 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -440,7 +440,8 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS);
} else if (OpCode == SPIRV::OpFunction) {
collectFuncNames(MI, &*F);
- } else if (OpCode == SPIRV::OpTypeForwardPointer) {
+ } else if (OpCode == SPIRV::OpTypeForwardPointer ||
+ TII->isInlineAsmDefInstr(MI)) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index d652b5de60808..7330f30653849 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -54,10 +54,11 @@ extern void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
} // namespace llvm
static bool isMetaInstrGET(unsigned Opcode) {
- return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_fID ||
- Opcode == SPIRV::GET_pID32 || Opcode == SPIRV::GET_pID64 ||
- Opcode == SPIRV::GET_vID || Opcode == SPIRV::GET_vfID ||
- Opcode == SPIRV::GET_vpID32 || Opcode == SPIRV::GET_vpID64;
+ return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_ID64 ||
+ Opcode == SPIRV::GET_fID || Opcode == SPIRV::GET_pID32 ||
+ Opcode == SPIRV::GET_pID64 || Opcode == SPIRV::GET_vID ||
+ Opcode == SPIRV::GET_vfID || Opcode == SPIRV::GET_vpID32 ||
+ Opcode == SPIRV::GET_vpID64;
}
static bool mayBeInserted(unsigned Opcode) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 9bff23dd96668..6df3f8ceb60dc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -215,6 +215,8 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
+ case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT: {
if (MI->getOperand(1).isReg()) {
if (MachineInstr *DefInstr =
@@ -457,12 +459,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
Ty = VectorType::get(ElemTy, NumElts, false);
}
insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
- } else if (MI.getOpcode() == TargetOpcode::G_TRUNC ||
- MI.getOpcode() == TargetOpcode::G_ZEXT ||
- MI.getOpcode() == TargetOpcode::G_PTRTOINT ||
- MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
- MI.getOpcode() == TargetOpcode::COPY ||
- MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) {
+ } else if (MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE) {
propagateSPIRVType(&MI, GR, MRI, MIB);
}
@@ -474,6 +471,24 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
}
for (MachineInstr *MI : ToErase)
MI->eraseFromParent();
+
+ // Address the case when IRTranslator introduces instructions with new
+ // registers without SPIRVType associated.
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_SEXT:
+ case TargetOpcode::G_ZEXT:
+ case TargetOpcode::G_PTRTOINT:
+ case TargetOpcode::COPY:
+ case TargetOpcode::G_ADDRSPACE_CAST:
+ propagateSPIRVType(&MI, GR, MRI, MIB);
+ break;
+ }
+ }
+ }
}
// Defined in SPIRVLegalizerInfo.cpp.
@@ -519,6 +534,115 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
}
}
+static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
+ const SPIRVSubtarget &ST,
+ MachineIRBuilder MIRBuilder) {
+ SmallVector<MachineInstr *> ToProcess;
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ if (isSpvIntrinsic(MI, Intrinsic::spv_inline_asm) ||
+ MI.getOpcode() == TargetOpcode::INLINEASM)
+ ToProcess.push_back(&MI);
+ }
+ }
+ unsigned Sz = ToProcess.size();
+ if (Sz == 0)
+ return;
+
+ if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly))
+ report_fatal_error("Inline assembly instructions require the "
+ "following SPIR-V extension: SPV_INTEL_inline_assembly",
+ false);
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ Register AsmTargetReg;
+ for (unsigned i = 0; i + 1 < Sz; i += 2) {
+ MachineInstr *I1 = ToProcess[i], *I2 = ToProcess[i + 1];
+ assert(isSpvIntrinsic(*I1, Intrinsic::spv_inline_asm) && I2->isInlineAsm());
+ MIRBuilder.setInsertPt(*I1->getParent(), *I1);
+
+ if (!AsmTargetReg.isValid()) {
+ // define vendor specific assembly target or dialect
+ AsmTargetReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ MRI.setRegClass(AsmTargetReg, &SPIRV::IDRegClass);
+ auto AsmTargetMIB =
+ MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg);
+ addStringImm(ST.getTargetTripleAsStr(), AsmTargetMIB);
+ }
+
+ // create types
+ const MDNode *IAMD = I1->getOperand(1).getMetadata();
+ FunctionType *FTy = cast<FunctionType>(getMDOperandAsType(IAMD, 0));
+ SmallVector<SPIRVType *, 4> ArgTypes;
+ for (const auto &ArgTy : FTy->params())
+ ArgTypes.push_back(GR->getOrCreateSPIRVType(ArgTy, MIRBuilder));
+ SPIRVType *RetType =
+ GR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder);
+ SPIRVType *FuncType = GR->getOrCreateOpTypeFunctionWithArgs(
+ FTy, RetType, ArgTypes, MIRBuilder);
+
+ // define vendor specific assembly instructions string
+ Register AsmReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ MRI.setRegClass(AsmReg, &SPIRV::IDRegClass);
+ auto AsmMIB = MIRBuilder.buildInstr(SPIRV::OpAsmINTEL)
+ .addDef(AsmReg)
+ .addUse(GR->getSPIRVTypeID(RetType))
+ .addUse(GR->getSPIRVTypeID(FuncType))
+ .addUse(AsmTargetReg);
+ const MDOperand &AsmStrMO = IAMD->getOperand(1);
+ const MDOperand &ConstrMO = IAMD->getOperand(2);
+ assert(isa<MDString>(AsmStrMO) && isa<MDString>(ConstrMO));
+ StringRef AsmStr = cast<MDString>(AsmStrMO)->getString();
+ addStringImm(AsmStr, AsmMIB);
+ StringRef Constr = cast<MDString>(ConstrMO)->getString();
+ addStringImm(Constr, AsmMIB);
+
+ // calls the inline assembly instruction
+ unsigned ExtraInfo = I2->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
+ if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
+ MIRBuilder.buildInstr(SPIRV::OpDecorate)
+ .addUse(AsmReg)
+ .addImm(static_cast<uint32_t>(SPIRV::Decoration::SideEffectsINTEL));
+ Register DefReg;
+ SmallVector<unsigned, 4> Ops;
+ unsigned StartOp = InlineAsm::MIOp_FirstOperand,
+ AsmDescOp = InlineAsm::MIOp_FirstOperand;
+ unsigned I2Sz = I2->getNumOperands();
+ for (unsigned Idx = StartOp; Idx != I2Sz; ++Idx) {
+ const MachineOperand &MO = I2->getOperand(Idx);
+ if (MO.isMetadata())
+ continue;
+ if (Idx == AsmDescOp && MO.isImm()) {
+ // compute the index of the next operand descriptor
+ const InlineAsm::Flag F(MO.getImm());
+ AsmDescOp += 1 + F.getNumOperandRegisters();
+ } else {
+ if (MO.isReg() && MO.isDef())
+ DefReg = MO.getReg();
+ else
+ Ops.push_back(Idx);
+ }
+ }
+ if (!DefReg.isValid()) {
+ DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ MRI.setRegClass(DefReg, &SPIRV::IDRegClass);
+ SPIRVType *VoidType = GR->getOrCreateSPIRVType(
+ Type::getVoidTy(MF.getFunction().getContext()), MIRBuilder);
+ GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
+ }
+ auto AsmCall = MIRBuilder.buildInstr(SPIRV::OpAsmCallINTEL)
+ .addDef(DefReg)
+ .addUse(GR->getSPIRVTypeID(RetType))
+ .addUse(AsmReg);
+ for (unsigned Idx : Ops)
+ AsmCall.add(I2->getOperand(Idx));
+ for (auto It = Ops.rbegin(), End = Ops.rend(); It != End; ++It)
+ I2->removeOperand(*It);
+ }
+ for (MachineInstr *MI : ToProcess)
+ MI->eraseFromParent();
+}
+
static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
SmallVector<MachineInstr *, 10> ToErase;
for (MachineBasicBlock &MBB : MF) {
@@ -673,6 +797,7 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
processInstrsWithTypeFolding(MF, GR, MIB);
removeImplicitFallthroughs(MF, MIB);
insertSpirvDecorations(MF, MIB);
+ insertInlineAsm(MF, GR, ST, MIB);
return true;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
index 32fbcf578827e..e385d9778eba2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
@@ -83,6 +83,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo {
TargetTriple.getArch() == Triple::spirv64;
}
bool isVulkanEnv() const { return TargetTriple.getArch() == Triple::spirv; }
+ const std::string &getTargetTripleAsStr() const { return TargetTriple.str(); }
VersionTuple getSPIRVVersion() const { return SPIRVVersion; };
bool isAtLeastSPIRVVer(VersionTuple VerToCompareTo) const;
bool isAtLeastOpenCLVer(VersionTuple VerToCompareTo) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 50d327179fa84..98cbd9d2c1f2e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -298,6 +298,7 @@ defm SPV_INTEL_optnone : ExtensionOperand<103>;
defm SPV_INTEL_function_pointers : ExtensionOperand<104>;
defm SPV_INTEL_variable_length_array : ExtensionOperand<105>;
defm SPV_INTEL_bfloat16_conversion : ExtensionOperand<106>;
+defm SPV_INTEL_inline_assembly : ExtensionOperand<107>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -458,6 +459,7 @@ defm BitInstructions : CapabilityOperand<6025, 0, 0, [SPV_KHR_bit_instructions],
defm ExpectAssumeKHR : CapabilityOperand<5629, 0, 0, [SPV_KHR_expect_assume], []>;
defm FunctionPointersINTEL : CapabilityOperand<5603, 0, 0, [SPV_INTEL_function_pointers], []>;
defm IndirectReferencesINTEL : CapabilityOperand<5604, 0, 0, [SPV_INTEL_function_pointers], []>;
+defm AsmINTEL : CapabilityOperand<5606, 0, 0, [SPV_INTEL_inline_assembly], []>;
defm GroupNonUniformRotateKHR : CapabilityOperand<6026, 0, 0, [SPV_KHR_subgroup_rotate], [GroupNonUniform]>;
defm AtomicFloat32AddEXT : CapabilityOperand<6033, 0, 0, [SPV_EXT_shader_atomic_float_add], []>;
defm AtomicFloat64AddEXT : CapabilityOperand<6034, 0, 0, [SPV_EXT_shader_atomic_float_add], []>;
@@ -1201,6 +1203,8 @@ defm UserSemantic : DecorationOperand<5635, 0, 0, [], []>;
defm RestrictPointerEXT : DecorationOperand<5355, 0, 0, [], [PhysicalStorageBufferAddressesEXT]>;
defm AliasedPointerEXT : DecorationOperand<5356, 0, 0, [], [PhysicalStorageBufferAddressesEXT]>;
defm ReferencedIndirectlyINTEL : DecorationOperand<5602, 0, 0, [], [IndirectReferencesINTEL]>;
+defm ClobberINTEL : DecorationOperand<5607, 0, 0, [SPV_INTEL_inline_assembly], [AsmINTEL]>;
+defm SideEffectsINTEL : DecorationOperand<5608, 0, 0, [SPV_INTEL_inline_assembly], [AsmINTEL]>;
defm ArgumentAttributeINTEL : DecorationOperand<6409, 0, 0, [], [FunctionPointersINTEL]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index 7d1429f7ef6ee..461bbb371f731 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -16,6 +16,7 @@ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:
target triple = "spir64-unknown-unknown"
define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) {
+ call void asm sideeffect "constcmd $0 $1", "r,r"(i32 123, double 42.0)
%i1 = load i32, ptr addrspace(1) %_arg_int
%i2 = load i8, ptr addrspace(1) %_arg_int
%f1 = load float, ptr addrspace(1) %_arg_float
@@ -40,13 +41,14 @@ define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_
store float %res_f1, ptr addrspace(1) %_arg_float
; inline asm: mixed floats
%res_f2 = call half asm sideeffect "fcmdext $0 $1 $2", "=r,r,r"(float 2.0, float %f1)
- store float %res_f1, ptr addrspace(1) %_arg_half
+ store half %res_f2, ptr addrspace(1) %_arg_half
; inline asm: mixed operands of different types
call i8 asm sideeffect "cmdext $0 $3 $1 $2", "=r,r,r,r"(float %f1, i32 123, i8 %i2)
; inline asm: mixed integers
%res_i2 = call i64 asm sideeffect "icmdext $0 $3 $1 $2", "=r,r,r,r"(i64 %_lng, i32 %i1, i8 %i2)
store i64 %res_i2, ptr addrspace(1) %_arg_int
; inline asm: constant arguments
- call void asm sideeffect "constcmd $0 $1", "i,i"(i32 123, double 42.0)
+ call void asm sideeffect "constcmd $0 $1", "r,r"(i32 123, double 42.0)
+; call void asm sideeffect "constcmd $0 $1", "i,i"(i32 123, double 42.0)
ret void
}
>From d342cdaf2610488c0fd8e37d49d3a76bbdc91f80 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Wed, 22 May 2024 04:13:49 -0700
Subject: [PATCH 3/7] add use of fp64
---
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 4 +++-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 3 ++-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 1 +
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp | 8 ++++----
llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td | 6 ++++--
6 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index 9a95cd8239234..2bd22bbd63169 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -91,7 +91,9 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0u, RC);
if (VT.isFloatingPoint())
- RC = VT.isVector() ? &SPIRV::vfIDRegClass : &SPIRV::fIDRegClass;
+ RC = VT.isVector() ? &SPIRV::vfIDRegClass
+ : (VT.getScalarSizeInBits() > 32 ? &SPIRV::fID64RegClass
+ : &SPIRV::fIDRegClass);
else if (VT.isInteger())
RC = VT.isVector() ? &SPIRV::vIDRegClass
: (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index c69d3fe1eb57b..12cf7613a45cf 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -257,7 +257,8 @@ void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool SPIRVInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_ID64 ||
- MI.getOpcode() == SPIRV::GET_fID || MI.getOpcode() == SPIRV::GET_pID32 ||
+ MI.getOpcode() == SPIRV::GET_fID || MI.getOpcode() == SPIRV::GET_fID64 ||
+ MI.getOpcode() == SPIRV::GET_pID32 ||
MI.getOpcode() == SPIRV::GET_pID64 || MI.getOpcode() == SPIRV::GET_vfID ||
MI.getOpcode() == SPIRV::GET_vID || MI.getOpcode() == SPIRV::GET_vpID32 ||
MI.getOpcode() == SPIRV::GET_vpID64) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index f420e46623e32..ab0e76b9f0ee9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -20,6 +20,7 @@ let isCodeGenOnly=1 in {
def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
+ def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
def GET_pID64: Pseudo<(outs pID64:$dst_id), (ins ANYID:$src)>;
def GET_vID: Pseudo<(outs vID:$dst_id), (ins ANYID:$src)>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index 7330f30653849..c3842f0266706 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -55,10 +55,10 @@ extern void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
static bool isMetaInstrGET(unsigned Opcode) {
return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_ID64 ||
- Opcode == SPIRV::GET_fID || Opcode == SPIRV::GET_pID32 ||
- Opcode == SPIRV::GET_pID64 || Opcode == SPIRV::GET_vID ||
- Opcode == SPIRV::GET_vfID || Opcode == SPIRV::GET_vpID32 ||
- Opcode == SPIRV::GET_vpID64;
+ Opcode == SPIRV::GET_fID || Opcode == SPIRV::GET_fID64 ||
+ Opcode == SPIRV::GET_pID32 || Opcode == SPIRV::GET_pID64 ||
+ Opcode == SPIRV::GET_vID || Opcode == SPIRV::GET_vfID ||
+ Opcode == SPIRV::GET_vpID32 || Opcode == SPIRV::GET_vpID64;
}
static bool mayBeInserted(unsigned Opcode) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
index 7f7f0f36ae5d3..e81d969564046 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
@@ -10,4 +10,4 @@
// as InstructionSelector RegClass checking code relies on them
def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
-def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, pID32, pID64, vID, vfID, vpID32, vpID64]>;
+def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
index 70bbe1da525e6..17f6ba59cc5de 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
@@ -31,6 +31,7 @@ let Namespace = "SPIRV" in {
def ID0 : Register<"ID0">;
def ID640 : Register<"ID640">;
def fID0 : Register<"fID0">;
+ def fID640 : Register<"fID640">;
def pID320 : Register<"pID320">;
def pID640 : Register<"pID640">;
def vID0 : Register<"vID0">;
@@ -41,6 +42,7 @@ let Namespace = "SPIRV" in {
def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
+ def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>;
def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>;
def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
@@ -50,9 +52,9 @@ let Namespace = "SPIRV" in {
def ANYID : RegisterClass<
"SPIRV",
- [i32, i64, f32, p32, p64, v2i32, v2f32, v2p32, v2p64],
+ [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
32,
- (add ID0, ID640, fID0, pID320, pID640, vID0, vfID0, vpID320, vpID640)>;
+ (add ID0, ID640, fID0, fID640, pID320, pID640, vID0, vfID0, vpID320, vpID640)>;
// A few instructions like OpName can take ids from both type and non-type
// instructions, so we need a super-class to allow for both to count as valid
>From d824caa0d087005ad1d0947de0ad77add84cea59 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Wed, 22 May 2024 07:26:17 -0700
Subject: [PATCH 4/7] inline asm ready, without a test case
---
llvm/docs/SPIRVUsage.rst | 2 +
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 3 +-
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 48 +++++++++++++++++--
llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 2 +
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 12 ++++-
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 25 ++++++----
.../SPV_INTEL_inline_assembly/inline_asm.ll | 27 +++++++----
8 files changed, 97 insertions(+), 24 deletions(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 0dfbffd6274e5..9f1e064dbdbdf 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -163,6 +163,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Allows to use the LinkOnceODR linkage type that lets a function or global variable to be merged with other functions or global variables of the same name when linkage occurs.
* - ``SPV_KHR_no_integer_wrap_decoration``
- Adds decorations to indicate that a given instruction does not cause integer wrapping.
+ * - ``SPV_KHR_shader_clock``
+ - Adds the extension cl_khr_kernel_clock.
* - ``SPV_KHR_subgroup_rotate``
- Adds a new instruction that enables rotating values across invocations within a subgroup.
* - ``SPV_KHR_uniform_group_instructions``
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 78997a8312b00..c93cbd43946d4 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -36,7 +36,8 @@ let TargetPrefix = "spv" in {
def int_spv_alloca : Intrinsic<[llvm_any_ty], []>;
def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty]>;
def int_spv_undef : Intrinsic<[llvm_i32_ty], []>;
- def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty]>;
+// def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty]>;
+ def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_vararg_ty]>;
// Expect, Assume Intrinsics
def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>;
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index b468b71cc0efb..a32adfca5ccbe 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -313,6 +313,41 @@ void SPIRVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
}
+/*
+void SPIRVInstPrinter::printStringImm(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNo).isReg() || OpNo >= MI->getNumOperands())
+ return;
+
+ unsigned StrStartIndex = OpNo;
+ std::string Str = getSPIRVStringOperand(*MI, StrStartIndex);
+ O << '"';
+ for (char c : Str) {
+ // Escape ", \n characters (might break for complex UTF-8).
+ if (c == '\n') {
+ O.write("\\n", 2);
+ } else {
+ if (c == '"')
+ O.write('\\');
+ O.write(c);
+ }
+ }
+ O << '"';
+
+ unsigned numOpsInString = (Str.size() / 4) + 1;
+ StrStartIndex += numOpsInString;
+
+ // Check for final Op of "OpDecorate %x %stringImm %linkageAttribute".
+ if (MI->getOpcode() == SPIRV::OpDecorate &&
+ MI->getOperand(1).getImm() ==
+ static_cast<unsigned>(Decoration::LinkageAttributes)) {
+ O << ' ';
+ printSymbolicOperand<OperandCategory::LinkageTypeOperand>(
+ MI, StrStartIndex, O);
+ }
+}
+*/
+
void SPIRVInstPrinter::printStringImm(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const unsigned NumOps = MI->getNumOperands();
@@ -321,14 +356,19 @@ void SPIRVInstPrinter::printStringImm(const MCInst *MI, unsigned OpNo,
if (MI->getOperand(StrStartIndex).isReg())
break;
- std::string Str = getSPIRVStringOperand(*MI, OpNo);
+ std::string Str = getSPIRVStringOperand(*MI, StrStartIndex);
if (StrStartIndex != OpNo)
O << ' '; // Add a space if we're starting a new string/argument.
O << '"';
for (char c : Str) {
- if (c == '"')
- O.write('\\'); // Escape " characters (might break for complex UTF-8).
- O.write(c);
+ // Escape ", \n characters (might break for complex UTF-8).
+ if (c == '\n') {
+ O.write("\\n", 2);
+ } else {
+ if (c == '"')
+ O.write('\\');
+ O.write(c);
+ }
}
O << '"';
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 09750667d3176..ff7cf9a92f40c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -659,6 +659,8 @@ Instruction *SPIRVEmitIntrinsics::visitCallInst(CallInst &Call) {
MDString::get(Ctx, IA->getConstraintString())};
SmallVector<Value *> Args = {
MetadataAsValue::get(Ctx, MDNode::get(Ctx, MDs))};
+ for (unsigned OpIdx = 0; OpIdx < Call.arg_size(); OpIdx++)
+ Args.push_back(Call.getArgOperand(OpIdx));
IRBuilder<> B(Call.getParent());
B.SetInsertPoint(&Call);
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index ab0e76b9f0ee9..7c9b84a48a2a7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -861,6 +861,6 @@ def OpGroupLogicalXorKHR: Op<6408, (outs ID:$res), (ins TYPE:$type, ID:$scope, i
def OpAsmTargetINTEL: Op<5609, (outs ID:$res), (ins StringImm:$str), "$res = OpAsmTargetINTEL $str">;
def OpAsmINTEL: Op<5610, (outs ID:$res), (ins TYPE:$type, TYPE:$asm_type, ID:$target,
StringImm:$asm, StringImm:$constraints),
- "$res = OpAsmINTEL $type $asm_type $target $asm $constraints">;
+ "$res = OpAsmINTEL $type $asm_type $target $asm">;
def OpAsmCallINTEL: Op<5611, (outs ID:$res), (ins TYPE:$type, ID:$asm, variable_ops),
"$res = OpAsmCallINTEL $type $asm">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index c8103ee01e3ca..f6b1fe7f0fbdc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -440,8 +440,8 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS);
} else if (OpCode == SPIRV::OpFunction) {
collectFuncNames(MI, &*F);
- } else if (OpCode == SPIRV::OpTypeForwardPointer ||
- TII->isInlineAsmDefInstr(MI)) {
+ } else if (OpCode == SPIRV::OpTypeForwardPointer/* ||
+ TII->isInlineAsmDefInstr(MI)*/) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false);
}
}
@@ -1152,6 +1152,14 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::VariableLengthArrayINTEL);
}
break;
+ case SPIRV::OpAsmTargetINTEL:
+ case SPIRV::OpAsmINTEL:
+ case SPIRV::OpAsmCallINTEL:
+ if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly)) {
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_inline_assembly);
+ Reqs.addCapability(SPIRV::Capability::AsmINTEL);
+ }
+ break;
default:
break;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 6df3f8ceb60dc..d340f2420ae2b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -568,6 +568,7 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
auto AsmTargetMIB =
MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg);
addStringImm(ST.getTargetTripleAsStr(), AsmTargetMIB);
+ GR->add(AsmTargetMIB.getInstr(), &MF, AsmTargetReg);
}
// create types
@@ -592,10 +593,9 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
const MDOperand &AsmStrMO = IAMD->getOperand(1);
const MDOperand &ConstrMO = IAMD->getOperand(2);
assert(isa<MDString>(AsmStrMO) && isa<MDString>(ConstrMO));
- StringRef AsmStr = cast<MDString>(AsmStrMO)->getString();
- addStringImm(AsmStr, AsmMIB);
- StringRef Constr = cast<MDString>(ConstrMO)->getString();
- addStringImm(Constr, AsmMIB);
+ addStringImm(cast<MDString>(AsmStrMO)->getString(), AsmMIB);
+ addStringImm(cast<MDString>(ConstrMO)->getString(), AsmMIB);
+ GR->add(AsmMIB.getInstr(), &MF, AsmReg);
// calls the inline assembly instruction
unsigned ExtraInfo = I2->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
@@ -634,10 +634,19 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
.addDef(DefReg)
.addUse(GR->getSPIRVTypeID(RetType))
.addUse(AsmReg);
- for (unsigned Idx : Ops)
- AsmCall.add(I2->getOperand(Idx));
- for (auto It = Ops.rbegin(), End = Ops.rend(); It != End; ++It)
- I2->removeOperand(*It);
+ //for (unsigned Idx : Ops)
+ // AsmCall.add(I2->getOperand(Idx));
+ //for (auto It = Ops.rbegin(), End = Ops.rend(); It != End; ++It)
+ // I2->removeOperand(*It);
+ unsigned IntrIdx = 1;
+ for (unsigned Idx : Ops) {
+ ++IntrIdx;
+ const MachineOperand& MO = I2->getOperand(Idx);
+ if (MO.isReg())
+ AsmCall.addUse(MO.getReg());
+ else
+ AsmCall.addUse(I1->getOperand(IntrIdx).getReg());
+ }
}
for (MachineInstr *MI : ToProcess)
MI->eraseFromParent();
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index 461bbb371f731..cf3448897f63e 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -4,10 +4,22 @@
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
; CHECK-ERROR: LLVM ERROR: requires the following SPIR-V extension: SPV_INTEL_inline_assembly
-; CHECK: Capability AsmINTEL
-; CHECK: Extension "SPV_INTEL_inline_assembly"
-; CHECK: Decorate SideEffectsINTEL
-; CHECK: AsmTargetINTEL "spir64-unknown-unknown"
+; CHECK: OpCapability AsmINTEL
+; CHECK: OpExtension "SPV_INTEL_inline_assembly"
+; CHECK-COUNT-8: OpDecorate %[[#]] SideEffectsINTEL
+; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spir64-unknown-unknown"
+; CHECK: %25 = OpAsmINTEL %[[#RetTy1:]] %[[#FunTy1:]] %[[#Dialect]] "" ""
+; CHECK: %26 = OpAsmINTEL %6 %13 %[[#Dialect]] "nop" ""
+; CHECK: %27 = OpAsmINTEL %6 %13 %[[#Dialect]] "" "~{cc},~{memory}"
+; CHECK: %28 = OpAsmINTEL %2 %14 %[[#Dialect]] "clobber_out $0" "=&r"
+; CHECK: %29 = OpAsmINTEL %2 %15 %[[#Dialect]] "icmd $0 $1" "=r,r"
+; CHECK: %30 = OpAsmINTEL %3 %16 %[[#Dialect]] "fcmd $0 $1" "=r,r"
+; CHECK: %31 = OpAsmINTEL %4 %17 %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r"
+; CHECK: %32 = OpAsmINTEL %11 %18 %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r"
+; CHECK: %33 = OpAsmINTEL %5 %19 %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r"
+; CHECK: %34 = OpAsmINTEL %6 %20 %[[#Dialect]] "constcmd $0 $1" "r,r"
+; CHECK: %35 = OpAsmINTEL %6 %20 %[[#Dialect]] "constcmd $0 $1" "i,i"
+
; CHECK: AsmINTEL
; CHECK: OpFunction
; CHECK: AsmCallINTEL
@@ -16,7 +28,6 @@ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:
target triple = "spir64-unknown-unknown"
define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) {
- call void asm sideeffect "constcmd $0 $1", "r,r"(i32 123, double 42.0)
%i1 = load i32, ptr addrspace(1) %_arg_int
%i2 = load i8, ptr addrspace(1) %_arg_int
%f1 = load float, ptr addrspace(1) %_arg_float
@@ -29,7 +40,7 @@ define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_
;; store half %r_struct2, ptr addrspace(1) %_arg_half
; inline asm
call void asm sideeffect "", ""()
- call void asm sideeffect "undefined\0A", ""()
+ call void asm sideeffect "nop", ""()
call void asm sideeffect "", "~{cc},~{memory}"()
%res_i0 = call i32 asm "clobber_out $0", "=&r"()
store i32 %res_i0, ptr addrspace(1) %_arg_int
@@ -48,7 +59,7 @@ define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_
%res_i2 = call i64 asm sideeffect "icmdext $0 $3 $1 $2", "=r,r,r,r"(i64 %_lng, i32 %i1, i8 %i2)
store i64 %res_i2, ptr addrspace(1) %_arg_int
; inline asm: constant arguments
- call void asm sideeffect "constcmd $0 $1", "r,r"(i32 123, double 42.0)
-; call void asm sideeffect "constcmd $0 $1", "i,i"(i32 123, double 42.0)
+ call void asm "constcmd $0 $1", "r,r"(i32 123, double 42.0)
+ call void asm "constcmd $0 $1", "i,i"(i32 123, double 42.0)
ret void
}
>From 515ec909fbdb12b3551928f4875bd0696593aa75 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Wed, 22 May 2024 09:30:44 -0700
Subject: [PATCH 5/7] add a test case
---
.../SPV_INTEL_inline_assembly/inline_asm.ll | 68 +++++++++++++------
1 file changed, 49 insertions(+), 19 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index cf3448897f63e..adf98ca1e9725 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -1,31 +1,61 @@
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - -filetype=obj | spirv-val %}
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_inline_assembly -o - -filetype=obj | spirv-val %}
; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-; CHECK-ERROR: LLVM ERROR: requires the following SPIR-V extension: SPV_INTEL_inline_assembly
+; CHECK-ERROR: Inline assembly instructions require the following SPIR-V extension: SPV_INTEL_inline_assembly
; CHECK: OpCapability AsmINTEL
; CHECK: OpExtension "SPV_INTEL_inline_assembly"
+
; CHECK-COUNT-8: OpDecorate %[[#]] SideEffectsINTEL
-; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spir64-unknown-unknown"
-; CHECK: %25 = OpAsmINTEL %[[#RetTy1:]] %[[#FunTy1:]] %[[#Dialect]] "" ""
-; CHECK: %26 = OpAsmINTEL %6 %13 %[[#Dialect]] "nop" ""
-; CHECK: %27 = OpAsmINTEL %6 %13 %[[#Dialect]] "" "~{cc},~{memory}"
-; CHECK: %28 = OpAsmINTEL %2 %14 %[[#Dialect]] "clobber_out $0" "=&r"
-; CHECK: %29 = OpAsmINTEL %2 %15 %[[#Dialect]] "icmd $0 $1" "=r,r"
-; CHECK: %30 = OpAsmINTEL %3 %16 %[[#Dialect]] "fcmd $0 $1" "=r,r"
-; CHECK: %31 = OpAsmINTEL %4 %17 %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r"
-; CHECK: %32 = OpAsmINTEL %11 %18 %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r"
-; CHECK: %33 = OpAsmINTEL %5 %19 %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r"
-; CHECK: %34 = OpAsmINTEL %6 %20 %[[#Dialect]] "constcmd $0 $1" "r,r"
-; CHECK: %35 = OpAsmINTEL %6 %20 %[[#Dialect]] "constcmd $0 $1" "i,i"
-; CHECK: AsmINTEL
-; CHECK: OpFunction
-; CHECK: AsmCallINTEL
+; CHECK-DAG: %[[#VoidTy:]] = OpTypeVoid
+; CHECK-DAG: %[[#Int8Ty:]] = OpTypeInt 8 0
+; CHECK-DAG: %[[#Int32Ty:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#Int64Ty:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#HalfTy:]] = OpTypeFloat 16
+; CHECK-DAG: %[[#FloatTy:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#DoubleTy:]] = OpTypeFloat 64
+
+; CHECK-DAG: OpTypeFunction %[[#VoidTy]] %[[#]] %[[#]] %[[#]] %[[#Int64Ty]]
+; CHECK-DAG: %[[#Fun1Ty:]] = OpTypeFunction %[[#VoidTy]]
+; CHECK-DAG: %[[#Fun2Ty:]] = OpTypeFunction %[[#Int32Ty]]
+; CHECK-DAG: %[[#Fun3Ty:]] = OpTypeFunction %[[#Int32Ty]] %[[#Int32Ty]]
+; CHECK-DAG: %[[#Fun4Ty:]] = OpTypeFunction %[[#FloatTy]] %[[#FloatTy]]
+; CHECK-DAG: %[[#Fun5Ty:]] = OpTypeFunction %[[#HalfTy]] %[[#FloatTy]] %[[#FloatTy]]
+; CHECK-DAG: %[[#Fun6Ty:]] = OpTypeFunction %[[#Int8Ty]] %[[#FloatTy]] %[[#Int32Ty]] %[[#Int8Ty]]
+; CHECK-DAG: %[[#Fun7Ty:]] = OpTypeFunction %[[#Int64Ty]] %[[#Int64Ty]] %[[#Int32Ty]] %[[#Int8Ty]]
+; CHECK-DAG: %[[#Fun8Ty:]] = OpTypeFunction %[[#VoidTy]] %[[#Int32Ty]] %[[#DoubleTy]]
-target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
-target triple = "spir64-unknown-unknown"
+; CHECK-DAG: %[[#Const2:]] = OpConstant %[[#FloatTy]] 2
+; CHECK-DAG: %[[#Const123:]] = OpConstant %[[#Int32Ty]] 123
+; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#DoubleTy:]] 42
+
+; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown"
+; CHECK: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" ""
+; CHECK: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" ""
+; CHECK: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}"
+; CHECK: %[[#Asm4:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun2Ty:]] %[[#Dialect]] "clobber_out $0" "=&r"
+; CHECK: %[[#Asm5:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun3Ty]] %[[#Dialect]] "icmd $0 $1" "=r,r"
+; CHECK: %[[#Asm6:]] = OpAsmINTEL %[[#FloatTy]] %[[#Fun4Ty]] %[[#Dialect]] "fcmd $0 $1" "=r,r"
+; CHECK: %[[#Asm7:]] = OpAsmINTEL %[[#HalfTy]] %[[#Fun5Ty]] %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r"
+; CHECK: %[[#Asm8:]] = OpAsmINTEL %[[#Int8Ty]] %[[#Fun6Ty]] %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r"
+; CHECK: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r"
+; CHECK: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r"
+; CHECK: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i"
+
+; CHECK: OpFunction
+; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm1]]
+; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm2]]
+; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm3]]
+; CHECK: OpAsmCallINTEL %[[#Int32Ty]] %[[#Asm4]]
+; CHECK: OpAsmCallINTEL %[[#Int32Ty]] %[[#Asm5]] %[[#]]
+; CHECK: OpAsmCallINTEL %[[#FloatTy]] %[[#Asm6]] %[[#]]
+; CHECK: OpAsmCallINTEL %[[#HalfTy]] %[[#Asm7]] %[[#Const2]] %[[#]]
+; CHECK: OpAsmCallINTEL %[[#Int8Ty]] %[[#Asm8]] %[[#]] %[[#Const123]] %[[#]]
+; CHECK: OpAsmCallINTEL %[[#Int64Ty]] %[[#Asm9]] %[[#]] %[[#]] %[[#]]
+; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm10]] %[[#Const123]] %[[#Const42]]
+; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm11]] %[[#Const123]] %[[#Const42]]
define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) {
%i1 = load i32, ptr addrspace(1) %_arg_int
>From 603df2577a58fa40ac2e092c25de8a8f7755cf31 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Thu, 23 May 2024 03:07:08 -0700
Subject: [PATCH 6/7] final version of inline assembly support
---
llvm/docs/SPIRVUsage.rst | 6 +-
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 3 +-
llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 26 ++-----
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 74 ++++++++++---------
.../SPV_INTEL_inline_assembly/inline_asm.ll | 6 +-
5 files changed, 54 insertions(+), 61 deletions(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 9f1e064dbdbdf..1f6157e53664a 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -163,8 +163,6 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Allows to use the LinkOnceODR linkage type that lets a function or global variable to be merged with other functions or global variables of the same name when linkage occurs.
* - ``SPV_KHR_no_integer_wrap_decoration``
- Adds decorations to indicate that a given instruction does not cause integer wrapping.
- * - ``SPV_KHR_shader_clock``
- - Adds the extension cl_khr_kernel_clock.
* - ``SPV_KHR_subgroup_rotate``
- Adds a new instruction that enables rotating values across invocations within a subgroup.
* - ``SPV_KHR_uniform_group_instructions``
@@ -337,6 +335,10 @@ SPIR-V backend, along with their descriptions and argument details.
- 32-bit Integer
- `[]`
- Generates an undefined value. Useful for optimizations and indicating uninitialized variables.
+ * - `int_spv_inline_asm`
+ - None
+ - `[Metadata, Metadata, Vararg]`
+ - Associates inline assembly features to inline assembly call instances by creating metadatas and preserving original arguments. Not emitted directly but used to support SPIR-V representation in LLVM IR.
* - `int_spv_assume`
- None
- `[1-bit Integer]`
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index c93cbd43946d4..90f12674d0470 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -36,8 +36,7 @@ let TargetPrefix = "spv" in {
def int_spv_alloca : Intrinsic<[llvm_any_ty], []>;
def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty]>;
def int_spv_undef : Intrinsic<[llvm_i32_ty], []>;
-// def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty]>;
- def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_vararg_ty]>;
+ def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_metadata_ty, llvm_vararg_ty]>;
// Expect, Assume Intrinsics
def int_spv_assume : Intrinsic<[], [llvm_i1_ty]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index ff7cf9a92f40c..ea53fe55e7ab5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -630,22 +630,6 @@ void SPIRVEmitIntrinsics::preprocessCompositeConstants(IRBuilder<> &B) {
}
}
-/*
- Constant *IATyVal = UndefValue::get(IA->getFunctionType());
- MetadataAsValue *IAtyArg = MetadataAsValue::get(
- Ctx, MDNode::get(Ctx, ValueAsMetadata::getConstant(IATyVal)));
-// MetadataAsValue *IAtyArg = MetadataAsValue::get(Ctx, ValueAsMetadata::get(&Call));
- MetadataAsValue *IAStr =
- MetadataAsValue::get(Ctx, MDString::get(Ctx, IA->getAsmString()));
- MetadataAsValue *IAConstr =
- MetadataAsValue::get(Ctx, MDString::get(Ctx, IA->getConstraintString()));
-// SmallVector<Value *> Args = {UndefValue::get(IntegerType::getInt8Ty(Ctx))};//, IAStr, IAStr, IAConstr};
- SmallVector<Value *> Args = {IAtyArg};//, IAStr, IAStr, IAConstr};
- IRBuilder<> B(Call.getParent());
- B.SetInsertPoint(&Call);
-// B.CreateIntrinsic(Intrinsic::spv_inline_asm, {IntegerType::getInt8Ty(Ctx)}, {Args});
-// works with def int_spv_inline_asm : Intrinsic<[], [llvm_any_ty]>; --> B.CreateIntrinsic(Intrinsic::spv_inline_asm, {IAtyArg->getType}, {Args});
-*/
Instruction *SPIRVEmitIntrinsics::visitCallInst(CallInst &Call) {
if (!Call.isInlineAsm())
return &Call;
@@ -653,12 +637,12 @@ Instruction *SPIRVEmitIntrinsics::visitCallInst(CallInst &Call) {
const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
LLVMContext &Ctx = F->getContext();
- Constant *IATyVal = UndefValue::get(IA->getFunctionType());
- ArrayRef<Metadata *> MDs = {ValueAsMetadata::getConstant(IATyVal),
- MDString::get(Ctx, IA->getAsmString()),
- MDString::get(Ctx, IA->getConstraintString())};
+ Constant *TyC = UndefValue::get(IA->getFunctionType());
+ MDString *ConstraintString = MDString::get(Ctx, IA->getConstraintString());
SmallVector<Value *> Args = {
- MetadataAsValue::get(Ctx, MDNode::get(Ctx, MDs))};
+ MetadataAsValue::get(Ctx,
+ MDNode::get(Ctx, ValueAsMetadata::getConstant(TyC))),
+ MetadataAsValue::get(Ctx, MDNode::get(Ctx, ConstraintString))};
for (unsigned OpIdx = 0; OpIdx < Call.arg_size(); OpIdx++)
Args.push_back(Call.getArgOperand(OpIdx));
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index d340f2420ae2b..85299a49a6b94 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -534,29 +534,13 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
}
}
-static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
- const SPIRVSubtarget &ST,
- MachineIRBuilder MIRBuilder) {
- SmallVector<MachineInstr *> ToProcess;
- for (MachineBasicBlock &MBB : MF) {
- for (MachineInstr &MI : MBB) {
- if (isSpvIntrinsic(MI, Intrinsic::spv_inline_asm) ||
- MI.getOpcode() == TargetOpcode::INLINEASM)
- ToProcess.push_back(&MI);
- }
- }
- unsigned Sz = ToProcess.size();
- if (Sz == 0)
- return;
-
- if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly))
- report_fatal_error("Inline assembly instructions require the "
- "following SPIR-V extension: SPV_INTEL_inline_assembly",
- false);
-
+static void
+insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
+ const SPIRVSubtarget &ST, MachineIRBuilder MIRBuilder,
+ const SmallVector<MachineInstr *> &ToProcess) {
MachineRegisterInfo &MRI = MF.getRegInfo();
Register AsmTargetReg;
- for (unsigned i = 0; i + 1 < Sz; i += 2) {
+ for (unsigned i = 0, Sz = ToProcess.size(); i + 1 < Sz; i += 2) {
MachineInstr *I1 = ToProcess[i], *I2 = ToProcess[i + 1];
assert(isSpvIntrinsic(*I1, Intrinsic::spv_inline_asm) && I2->isInlineAsm());
MIRBuilder.setInsertPt(*I1->getParent(), *I1);
@@ -590,11 +574,13 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
.addUse(GR->getSPIRVTypeID(RetType))
.addUse(GR->getSPIRVTypeID(FuncType))
.addUse(AsmTargetReg);
- const MDOperand &AsmStrMO = IAMD->getOperand(1);
- const MDOperand &ConstrMO = IAMD->getOperand(2);
- assert(isa<MDString>(AsmStrMO) && isa<MDString>(ConstrMO));
- addStringImm(cast<MDString>(AsmStrMO)->getString(), AsmMIB);
- addStringImm(cast<MDString>(ConstrMO)->getString(), AsmMIB);
+ // inline asm string:
+ addStringImm(I2->getOperand(InlineAsm::MIOp_AsmString).getSymbolName(),
+ AsmMIB);
+ // inline asm constraint string:
+ addStringImm(cast<MDString>(I1->getOperand(2).getMetadata()->getOperand(0))
+ ->getString(),
+ AsmMIB);
GR->add(AsmMIB.getInstr(), &MF, AsmReg);
// calls the inline assembly instruction
@@ -631,17 +617,13 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
}
auto AsmCall = MIRBuilder.buildInstr(SPIRV::OpAsmCallINTEL)
- .addDef(DefReg)
- .addUse(GR->getSPIRVTypeID(RetType))
- .addUse(AsmReg);
- //for (unsigned Idx : Ops)
- // AsmCall.add(I2->getOperand(Idx));
- //for (auto It = Ops.rbegin(), End = Ops.rend(); It != End; ++It)
- // I2->removeOperand(*It);
- unsigned IntrIdx = 1;
+ .addDef(DefReg)
+ .addUse(GR->getSPIRVTypeID(RetType))
+ .addUse(AsmReg);
+ unsigned IntrIdx = 2;
for (unsigned Idx : Ops) {
++IntrIdx;
- const MachineOperand& MO = I2->getOperand(Idx);
+ const MachineOperand &MO = I2->getOperand(Idx);
if (MO.isReg())
AsmCall.addUse(MO.getReg());
else
@@ -652,6 +634,28 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
MI->eraseFromParent();
}
+static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
+ const SPIRVSubtarget &ST,
+ MachineIRBuilder MIRBuilder) {
+ SmallVector<MachineInstr *> ToProcess;
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ if (isSpvIntrinsic(MI, Intrinsic::spv_inline_asm) ||
+ MI.getOpcode() == TargetOpcode::INLINEASM)
+ ToProcess.push_back(&MI);
+ }
+ }
+ if (ToProcess.size() == 0)
+ return;
+
+ if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly))
+ report_fatal_error("Inline assembly instructions require the "
+ "following SPIR-V extension: SPV_INTEL_inline_assembly",
+ false);
+
+ insertInlineAsmProcess(MF, GR, ST, MIRBuilder, ToProcess);
+}
+
static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
SmallVector<MachineInstr *, 10> ToErase;
for (MachineBasicBlock &MBB : MF) {
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index adf98ca1e9725..3c1d622b39db7 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -32,6 +32,8 @@
; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#DoubleTy:]] 42
; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown"
+; CHECK-NO: OpAsmTargetINTEL
+
; CHECK: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" ""
; CHECK: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" ""
; CHECK: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}"
@@ -43,6 +45,7 @@
; CHECK: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r"
; CHECK: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r"
; CHECK: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i"
+; CHECK-NO: OpAsmINTEL
; CHECK: OpFunction
; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm1]]
@@ -56,6 +59,7 @@
; CHECK: OpAsmCallINTEL %[[#Int64Ty]] %[[#Asm9]] %[[#]] %[[#]] %[[#]]
; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm10]] %[[#Const123]] %[[#Const42]]
; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm11]] %[[#Const123]] %[[#Const42]]
+; CHECK-NO: OpAsmCallINTEL
define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) {
%i1 = load i32, ptr addrspace(1) %_arg_int
@@ -88,7 +92,7 @@ define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_
; inline asm: mixed integers
%res_i2 = call i64 asm sideeffect "icmdext $0 $3 $1 $2", "=r,r,r,r"(i64 %_lng, i32 %i1, i8 %i2)
store i64 %res_i2, ptr addrspace(1) %_arg_int
- ; inline asm: constant arguments
+ ; inline asm: constant arguments, misc constraints
call void asm "constcmd $0 $1", "r,r"(i32 123, double 42.0)
call void asm "constcmd $0 $1", "i,i"(i32 123, double 42.0)
ret void
>From d6e79965c846883bee09ecb16a0737e73ca897f9 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Thu, 23 May 2024 03:48:57 -0700
Subject: [PATCH 7/7] minor format
---
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 3 +--
llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 2 +-
.../extensions/SPV_INTEL_inline_assembly/inline_asm.ll | 6 ------
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index f6b1fe7f0fbdc..c86ab285f354f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -440,8 +440,7 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS);
} else if (OpCode == SPIRV::OpFunction) {
collectFuncNames(MI, &*F);
- } else if (OpCode == SPIRV::OpTypeForwardPointer/* ||
- TII->isInlineAsmDefInstr(MI)*/) {
+ } else if (OpCode == SPIRV::OpTypeForwardPointer) {
collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
index e385d9778eba2..211216488db79 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h
@@ -15,8 +15,8 @@
#include "SPIRVCallLowering.h"
#include "SPIRVFrameLowering.h"
-#include "SPIRVInlineAsmLowering.h"
#include "SPIRVISelLowering.h"
+#include "SPIRVInlineAsmLowering.h"
#include "SPIRVInstrInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
index 3c1d622b39db7..449dd71954500 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
@@ -66,12 +66,6 @@ define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_
%i2 = load i8, ptr addrspace(1) %_arg_int
%f1 = load float, ptr addrspace(1) %_arg_float
%h1 = load half, ptr addrspace(1) %_arg_half
-; ; inline asm: complex result
-; call { i64, half } asm sideeffect "structcmd_nop", "=r,=r"()
-; %r_struct = call { i64, half } asm sideeffect "structcmd $0 $0 $1 $1", "=r,=r,0,1"(i64 123, half %h1)
-;; %r_struct1 = extractvalue { i64, half } %r_struct, 0
-;; %r_struct2 = extractvalue { i64, half } %r_struct, 1
-;; store half %r_struct2, ptr addrspace(1) %_arg_half
; inline asm
call void asm sideeffect "", ""()
call void asm sideeffect "nop", ""()
More information about the llvm-commits
mailing list