[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 02:58:28 PDT 2024
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@@ -5456,43 +5444,32 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
if ((Size % 32) == 0) {
SmallVector<Register, 2> PartialRes;
unsigned NumParts = Size / 32;
- auto IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
+ bool IsS16Vec = Ty.isVector() && Ty.getElementType() == S16;
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arsenm wrote:
Better to track this as the LLT to use for the pieces, rather than making it this conditional thing. This will simplify improved pointer handling in the future
https://github.com/llvm/llvm-project/pull/89217
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