[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)
Vikram Hegde via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 02:09:12 PDT 2024
vikramRH wrote:
updated the GIsel legalizer, I still have couple of questions for SDAG case though,
1. What's the proper way to legalize f16 and bf16 for SDAG case without bitcasts ? (I would think "fp_extend -> LaneOp -> Fptrunc" is wrong)
2. For scalar cases such as i64, f64, i128 .. (i.e 32 bit multiples), I guess bitcast to vectors (v2i32, v2f32, v4i32) is unavoidable since "UnrollVectorOp" wouldn't work otherwise. any alternalte suggestions here ?
https://github.com/llvm/llvm-project/pull/89217
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