[llvm] [AArch64][SVE2] UZP should only have one result (PR #93041)

[Miguel Saldivar via llvm-commits]

Saldivarcher wrote:

@davemgreen I can add one, I had a reproducer in the issue I created. Here it is:
```llvm
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"

define void @main(ptr %0) {
"file t13_206.f90, line 27, bb4133118":
  %1 = bitcast <vscale x 2 x i64> zeroinitializer to <vscale x 4 x i32>
  %r2689 = extractelement <vscale x 4 x i32> %1, i64 0
  %r2690 = insertelement <2 x i32> zeroinitializer, i32 %r2689, i64 0
  %2 = bitcast <vscale x 2 x i64> zeroinitializer to <vscale x 4 x i32>
  %r2692 = extractelement <vscale x 4 x i32> %2, i64 2
  %r2693 = insertelement <2 x i32> %r2690, i32 %r2692, i64 1
  %r2696 = sub <2 x i32> zeroinitializer, %r2693
  %r2697 = extractelement <2 x i32> %r2696, i64 0
  %r2698 = sext i32 %r2697 to i64
  %r2699 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %r2698, i64 0
  %r2700 = extractelement <2 x i32> %r2696, i64 1
  %r2701 = sext i32 %r2700 to i64
  %r2702 = insertelement <vscale x 2 x i64> %r2699, i64 %r2701, i64 0
  store <vscale x 2 x i64> %r2702, ptr %0, align 16
  ret void
}
```

https://github.com/llvm/llvm-project/pull/93041