[llvm] c0de13b - [GISel][RISCV] Legalize shifts with non-trivial shamt types (#93019)
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Wed May 22 08:36:38 PDT 2024
Author: Yingwei Zheng
Date: 2024-05-22T23:36:34+08:00
New Revision: c0de13b05f9905dbbc582d234214081dd410db1d
URL: https://github.com/llvm/llvm-project/commit/c0de13b05f9905dbbc582d234214081dd410db1d
DIFF: https://github.com/llvm/llvm-project/commit/c0de13b05f9905dbbc582d234214081dd410db1d.diff
LOG: [GISel][RISCV] Legalize shifts with non-trivial shamt types (#93019)
This patch widens the illegal shamt type `i48` -> `i64` to fix
legalization failure: https://godbolt.org/z/4zMTnoW7h
Added:
llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index e3d74cef7e7fc..a1d3aadb816ab 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -141,7 +141,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(1, s32, sXLen)
.clampScalar(0, s32, sXLen)
- .minScalarSameAs(1, 0);
+ .minScalarSameAs(1, 0)
+ .widenScalarToNextPow2(1);
auto &ExtActions =
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
index 8cbae0fa0173e..43318118f09c5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
@@ -336,3 +336,29 @@ body: |
PseudoRET implicit $x10
...
+---
+name: lshr_i32_i48
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: lshr_i32_i48
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s48) = G_TRUNC %1(s64)
+ %2:_(s48) = G_CONSTANT i48 16
+ %6:_(s32) = G_TRUNC %0(s48)
+ %7:_(s32) = G_LSHR %6, %2(s48)
+ %5:_(s64) = G_ANYEXT %7(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
new file mode 100644
index 0000000000000..b75cbf8e871a1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV64
+
+define i16 @test_lshr_i48(i48 %x) {
+; RV32-LABEL: test_lshr_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a0, a0, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_lshr_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 16
+; RV64-NEXT: ret
+ %lshr = lshr i48 %x, 16
+ %trunc = trunc i48 %lshr to i16
+ ret i16 %trunc
+}
+
+define i16 @test_ashr_i48(i48 %x) {
+; RV32-LABEL: test_ashr_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: srai a0, a0, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_ashr_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 16
+; RV64-NEXT: ret
+ %ashr = ashr i48 %x, 16
+ %trunc = trunc i48 %ashr to i16
+ ret i16 %trunc
+}
+
+define i16 @test_shl_i48(i48 %x) {
+; RV32-LABEL: test_shl_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a0, a0, 8
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_shl_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 8
+; RV64-NEXT: ret
+ %shl = shl i48 %x, 8
+ %trunc = trunc i48 %shl to i16
+ ret i16 %trunc
+}
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