[llvm] [AArch64][SVE2] UZP should only have one result (PR #93041)

[Miguel Saldivar via llvm-commits]

https://github.com/Saldivarcher created https://github.com/llvm/llvm-project/pull/93041

`UZP1` and `UZP2` are only expecting one result value, so this `getNode` call should be updated to match that.

This is in response to #92779. 



>From 12025be115936a7b7a855a1530b1972ba005dda5 Mon Sep 17 00:00:00 2001
From: Miguel Saldivar <miguel.saldivar at hpe.com>
Date: Wed, 22 May 2024 09:51:18 -0500
Subject: [PATCH] [AArch64][SVE2] UZP should only have one result

`UZP1` and `UZP2` are only expecting one result value, so this `getNode`
call should be updated to match that.
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e31a27e9428e8..bbc896dac77fa 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13530,11 +13530,9 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
                       DAG.getConstant(NumElts, dl, MVT::i64));
 
       if (Even && !Odd)
-        return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS,
-                           RHS);
+        return DAG.getNode(AArch64ISD::UZP1, dl, VT, LHS, RHS);
       if (Odd && !Even)
-        return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS,
-                           RHS);
+        return DAG.getNode(AArch64ISD::UZP2, dl, VT, LHS, RHS);
     }
   }