[llvm] [GISel][RISCV] Legalize shifts with non-trivial shamt types (PR #93019)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Wed May 22 05:17:31 PDT 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/93019
>From 2c4836d03a3ab0046970849932abe02241a98f83 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Wed, 22 May 2024 19:07:15 +0800
Subject: [PATCH 1/2] [GISel][RISCV] Legalize shifts with non-trivial shamt
types
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 3 ++-
.../legalizer/legalize-lshr-rv64.mir | 26 +++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index c73fe2c6cecbe..606569caada23 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -137,7 +137,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(1, s32, sXLen)
.clampScalar(0, s32, sXLen)
- .minScalarSameAs(1, 0);
+ .minScalarSameAs(1, 0)
+ .widenScalarToNextPow2(1);
auto &ExtActions =
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
index 8cbae0fa0173e..43318118f09c5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
@@ -336,3 +336,29 @@ body: |
PseudoRET implicit $x10
...
+---
+name: lshr_i32_i48
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: lshr_i32_i48
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s48) = G_TRUNC %1(s64)
+ %2:_(s48) = G_CONSTANT i48 16
+ %6:_(s32) = G_TRUNC %0(s48)
+ %7:_(s32) = G_LSHR %6, %2(s48)
+ %5:_(s64) = G_ANYEXT %7(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
>From f4b6633b7a3f69971469dfc70a6433ed80bb8e06 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Wed, 22 May 2024 19:40:43 +0800
Subject: [PATCH 2/2] [GISel][RISCV] Add some IR tests. NFC.
---
llvm/test/CodeGen/RISCV/GlobalISel/shift.ll | 48 +++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
new file mode 100644
index 0000000000000..b75cbf8e871a1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV64
+
+define i16 @test_lshr_i48(i48 %x) {
+; RV32-LABEL: test_lshr_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a0, a0, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_lshr_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 16
+; RV64-NEXT: ret
+ %lshr = lshr i48 %x, 16
+ %trunc = trunc i48 %lshr to i16
+ ret i16 %trunc
+}
+
+define i16 @test_ashr_i48(i48 %x) {
+; RV32-LABEL: test_ashr_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: srai a0, a0, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_ashr_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: sraiw a0, a0, 16
+; RV64-NEXT: ret
+ %ashr = ashr i48 %x, 16
+ %trunc = trunc i48 %ashr to i16
+ ret i16 %trunc
+}
+
+define i16 @test_shl_i48(i48 %x) {
+; RV32-LABEL: test_shl_i48:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a0, a0, 8
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_shl_i48:
+; RV64: # %bb.0:
+; RV64-NEXT: slliw a0, a0, 8
+; RV64-NEXT: ret
+ %shl = shl i48 %x, 8
+ %trunc = trunc i48 %shl to i16
+ ret i16 %trunc
+}
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