[llvm] [AMDGPU] Copy Defs and Uses from Pseudo to Real Instructions (PR #93004)
Fabian Ritter via llvm-commits
llvm-commits at lists.llvm.org
Wed May 22 01:18:53 PDT 2024
https://github.com/ritter-x2a created https://github.com/llvm/llvm-project/pull/93004
Currently, the tablegen files that generate the instruction definitions in lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc often only include implicit operands for the architecture-independent pseudo instructions, but not for the corresponding real instructions. The missing implicit operands (most prominently: the EXEC mask) do not affect code generation, since that operates on pseudo instructions, but they are problematic when working with real instructions, e.g., as a decoding result from the MC layer.
This patch copies the implicit Defs and Uses from pseudo instructions to the corresponding real instructions, so that implicit operands are also defined for real instructions.
Addresses issue #89830.
>From 0cde3c41c6ff0a4e386d05c09129e3aa508297e2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter <fabian.ritter at amd.com>
Date: Wed, 22 May 2024 03:48:34 -0400
Subject: [PATCH] [AMDGPU] Copy Defs and Uses from Pseudo to Real Instructions
Currently, the tablegen files that generate the instruction definitions
in lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc often only include implicit
operands for the architecture-independent pseudo instructions, but not
for the corresponding real instructions. The missing implicit operands
(most prominently: the EXEC mask) do not affect code generation, since
that operates on pseudo instructions, but they are problematic when
working with real instructions, e.g., as a decoding result from the MC
layer.
This patch copies the implicit Defs and Uses from pseudo instructions to
the corresponding real instructions, so that implicit operands are also
defined for real instructions.
Addresses issue #89830.
---
llvm/lib/Target/AMDGPU/BUFInstructions.td | 6 ++++++
llvm/lib/Target/AMDGPU/DSInstructions.td | 2 ++
llvm/lib/Target/AMDGPU/FLATInstructions.td | 4 ++++
llvm/lib/Target/AMDGPU/SMInstructions.td | 2 ++
llvm/lib/Target/AMDGPU/SOPInstructions.td | 10 ++++++++++
llvm/lib/Target/AMDGPU/VOPInstructions.td | 6 ++++++
6 files changed, 30 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 8eaa113ac1816..f419f0b17352f 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -137,6 +137,8 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let mayStore = ps.mayStore;
let IsAtomicRet = ps.IsAtomicRet;
let IsAtomicNoRet = ps.IsAtomicNoRet;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
bits<12> offset;
bits<5> cpol;
@@ -351,6 +353,8 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let IsAtomicNoRet = ps.IsAtomicNoRet;
let VALU = ps.VALU;
let LGKM_CNT = ps.LGKM_CNT;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
bits<12> offset;
bits<5> cpol;
@@ -2392,6 +2396,8 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let LGKM_CNT = ps.LGKM_CNT;
let MUBUF = ps.MUBUF;
let MTBUF = ps.MTBUF;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
bits<24> offset;
bits<8> vaddr;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index f2825c48fceca..19bb4300531cf 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -71,6 +71,8 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let mayStore = ps.mayStore;
let IsAtomicRet = ps.IsAtomicRet;
let IsAtomicNoRet = ps.IsAtomicNoRet;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 377d48a48e9b9..154a7401bd6c0 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -102,6 +102,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let VM_CNT = ps.VM_CNT;
let LGKM_CNT = ps.LGKM_CNT;
let VALU = ps.VALU;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
// encoding fields
bits<8> vaddr;
@@ -165,6 +167,8 @@ class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let VM_CNT = ps.VM_CNT;
let LGKM_CNT = ps.LGKM_CNT;
let VALU = ps.VALU;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
bits<7> saddr;
bits<8> vdst;
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 40ba47f887710..1f1f86583b233 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -71,6 +71,8 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
let AsmMatchConverter = ps.AsmMatchConverter;
let IsAtomicRet = ps.IsAtomicRet;
let IsAtomicNoRet = ps.IsAtomicNoRet;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
let TSFlags = ps.TSFlags;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 394a5ed991bce..aee518680a607 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -65,6 +65,8 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
let isCall = ps.isCall;
let isBranch = ps.isBranch;
let isBarrier = ps.isBarrier;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
// encoding
bits<7> sdst;
@@ -570,6 +572,8 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
let mayStore = ps.mayStore;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
// encoding
bits<7> sdst;
@@ -985,6 +989,8 @@ class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :
let isTerminator = ps.isTerminator;
let isReturn = ps.isReturn;
let isBarrier = ps.isBarrier;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
// encoding
bits<7> sdst;
@@ -1245,6 +1251,8 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
// encoding
bits<8> src0;
@@ -1440,6 +1448,8 @@ class SOPP_Real<SOPP_Pseudo ps, string name = ps.Mnemonic> :
let isCall = ps.isCall;
let isBranch = ps.isBranch;
let isBarrier = ps.isBarrier;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
bits <16> simm16;
}
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index f45ab9bf46db1..5d1573d8dec19 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -657,6 +657,8 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
@@ -691,6 +693,8 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
@@ -895,6 +899,8 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
+ let Uses = ps.Uses;
+ let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
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