[llvm] [PowerPC] handle toc-data in load selection of fast-isel (PR #91916)
Chen Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue May 21 18:18:24 PDT 2024
https://github.com/chenzheng1030 updated https://github.com/llvm/llvm-project/pull/91916
>From 2dce53e92ed6742c4b7c581ca8c8db9afbb0d587 Mon Sep 17 00:00:00 2001
From: Chen Zheng <czhengsz at cn.ibm.com>
Date: Mon, 13 May 2024 02:13:53 -0400
Subject: [PATCH 1/2] [PowerPC] handle toc-data in load selection of fast-isel
---
llvm/lib/Target/PowerPC/PPCFastISel.cpp | 14 +++++++-------
llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll | 3 +--
llvm/test/CodeGen/PowerPC/toc-data.ll | 8 ++++----
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 6e31cdae84767..735050641adff 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -2074,16 +2074,15 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
if (GV->isThreadLocal())
return 0;
- // If the global has the toc-data attribute then fallback to DAG-ISEL.
- if (TM.getTargetTriple().isOSAIX())
- if (const GlobalVariable *Var = dyn_cast_or_null<GlobalVariable>(GV))
- if (Var->hasAttribute("toc-data"))
- return false;
-
PPCFuncInfo->setUsesTOCBasePtr();
+ bool IsAIXTocData = TM.getTargetTriple().isOSAIX() &&
+ isa<GlobalVariable>(GV) &&
+ cast<GlobalVariable>(GV)->hasAttribute("toc-data");
+
// For small code model, generate a simple TOC load.
if (CModel == CodeModel::Small)
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtoc),
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc),
DestReg)
.addGlobalAddress(GV)
.addReg(PPC::X2);
@@ -2101,6 +2100,7 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
if (Subtarget->isGVIndirectSymbol(GV)) {
+ assert(!IsAIXTocData && "TOC data should always be direct.");
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocL),
DestReg).addGlobalAddress(GV).addReg(HighPartReg);
} else {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll b/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
index 5a7fcd1d0ddd4..7533c5f8b3520 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
@@ -11,8 +11,7 @@ define signext i32 @foo() #1 {
; SMALL-LABEL: foo:
; SMALL: # %bb.0: # %entry
; SMALL-NEXT: la 3, a[TD](2)
-; SMALL-NEXT: lwz 3, 0(3)
-; SMALL-NEXT: extsw 3, 3
+; SMALL-NEXT: lwa 3, 0(3)
; SMALL-NEXT: blr
entry:
%0 = load i32, ptr @a, align 4
diff --git a/llvm/test/CodeGen/PowerPC/toc-data.ll b/llvm/test/CodeGen/PowerPC/toc-data.ll
index 7f7afe76cfcde..b2bb4abc5e58e 100644
--- a/llvm/test/CodeGen/PowerPC/toc-data.ll
+++ b/llvm/test/CodeGen/PowerPC/toc-data.ll
@@ -45,8 +45,8 @@ define dso_local void @write_int(i32 signext %in) {
; CHECK64-NOOPT: name: write_int
; CHECK64-NOOPT: %[[SUBREG:[0-9]+]]:gprc = COPY %{{[0-9]}}.sub_32
-; CHECK64-NOOPT: %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2 :: (load (s64) from got)
-; CHECK64-NOOPT: STW %[[SUBREG]], 0, killed %[[ADDR]] :: (store (s32) into @i)
+; CHECK64-NOOPT: %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
+; CHECK64-NOOPT: STW %[[SUBREG]], 0, %[[ADDR]]
; TEST64: .write_int:
; TEST64: la 4, i[TD](2)
@@ -117,7 +117,7 @@ define dso_local float @read_float() {
; CHECK64-NOOPT: name: read_float
; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
-; CHECK64-NOOPT: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]]
+; CHECK64-NOOPT: %{{[0-9]+}}:f4rc = LFS 0, %[[SCRATCH]]
; TEST64: .read_float:
; TEST64: la 3, f[TD](2)
@@ -183,7 +183,7 @@ define dso_local nonnull ptr @addr() {
; CHECK64-NEXT: $x3 = COPY %[[SCRATCH]]
; CHECK64-NOOPT: name: addr
-; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
+; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
; CHECK64-NOOPT: $x3 = COPY %[[SCRATCH]]
; TEST64: .addr
>From a570c490b8b8ef9a29c4de428f00d12154bacb3f Mon Sep 17 00:00:00 2001
From: Chen Zheng <czhengsz at cn.ibm.com>
Date: Tue, 21 May 2024 21:18:04 -0400
Subject: [PATCH 2/2] add test for large code model
---
llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll b/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
index 7533c5f8b3520..08dad1b495e2f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tocdata-fastisel.ll
@@ -1,9 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -fast-isel -verify-machineinstrs \
; RUN: -code-model=small | FileCheck %s --check-prefix=SMALL
-
-;; FIXME: when toc data for 64 big large code model is supported,
-;; add a run line for large code model too.
+; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -fast-isel -verify-machineinstrs \
+; RUN: -code-model=large | FileCheck %s --check-prefix=LARGE
@a = global i32 0, align 4 #0
@@ -13,6 +12,13 @@ define signext i32 @foo() #1 {
; SMALL-NEXT: la 3, a[TD](2)
; SMALL-NEXT: lwa 3, 0(3)
; SMALL-NEXT: blr
+;
+; LARGE-LABEL: foo:
+; LARGE: # %bb.0: # %entry
+; LARGE-NEXT: addis 3, a[TD]@u(2)
+; LARGE-NEXT: addi 3, 3, a[TD]@toc at l
+; LARGE-NEXT: lwa 3, 0(3)
+; LARGE-NEXT: blr
entry:
%0 = load i32, ptr @a, align 4
ret i32 %0
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