[llvm] [RISCV] Do not check PostRAScheduler in enablePostRAScheduler (PR #92781)

[Craig Topper via llvm-commits]

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@@ -230,6 +230,7 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
                                        FeatureStdExtZba,
                                        FeatureStdExtZbb],
                                       [TuneSiFive7,
+                                       FeaturePostRAScheduler,
                                        TuneDLenFactor2]>;
 
 def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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topperc wrote:

What about P450 and P670?

https://github.com/llvm/llvm-project/pull/92781