[llvm] [AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (PR #92130)

David Green via llvm-commits llvm-commits at lists.llvm.org
Tue May 21 15:02:28 PDT 2024


================
@@ -2906,9 +2927,18 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
     const LLT ValTy = MRI.getType(ValReg);
     const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
 
+    if (ValTy.isScalableVector()) {
+        assert(STI.hasSVE() 
+             && "Load/Store register operand is scalable vector "
+                "while SVE is not supported by the target");
+    }
----------------
davemgreen wrote:

```
assert((!ValTy.isScalableVector() || STI.hasSVE()) &&
           "Load/Store register operand is scalable vector while SVE is not "
           "supported by the target");
```

https://github.com/llvm/llvm-project/pull/92130


More information about the llvm-commits mailing list