[llvm] [RISCV] Enable early if-conversion (PR #92959)

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``````````bash
git-clang-format --diff 7273ad123850a7b44c0625d098ebb49153bf855a ba0bf89c2a1636b258d551c2dc96594879b8ddb7 -- llvm/lib/CodeGen/EarlyIfConversion.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 0cd7b3f405..fcf8ab5838 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1446,22 +1446,27 @@ RISCVInstrInfo::optimizeSelect(MachineInstr &MI,
   return NewMI;
 }
 
-int RISCVInstrInfo::getICmpCost(unsigned CC, const TargetSchedModel &SchedModel) const {
+int RISCVInstrInfo::getICmpCost(unsigned CC,
+                                const TargetSchedModel &SchedModel) const {
   switch (CC) {
-    default:
-      llvm_unreachable("Unknown condition code!");
-    case RISCVCC::COND_LT:
-      return SchedModel.computeInstrLatency(RISCV::SLT);
-    case RISCVCC::COND_LTU:
-      return SchedModel.computeInstrLatency(RISCV::SLTU);
-    case RISCVCC::COND_EQ:
-      return SchedModel.computeInstrLatency(RISCV::XOR) + SchedModel.computeInstrLatency(RISCV::SLTIU);
-    case RISCVCC::COND_NE:
-      return SchedModel.computeInstrLatency(RISCV::XOR) + SchedModel.computeInstrLatency(RISCV::SLTU);
-    case RISCVCC::COND_GE:
-      return SchedModel.computeInstrLatency(RISCV::XORI) + SchedModel.computeInstrLatency(RISCV::SLT);
-    case RISCVCC::COND_GEU:
-      return SchedModel.computeInstrLatency(RISCV::XORI) + SchedModel.computeInstrLatency(RISCV::SLTU);
+  default:
+    llvm_unreachable("Unknown condition code!");
+  case RISCVCC::COND_LT:
+    return SchedModel.computeInstrLatency(RISCV::SLT);
+  case RISCVCC::COND_LTU:
+    return SchedModel.computeInstrLatency(RISCV::SLTU);
+  case RISCVCC::COND_EQ:
+    return SchedModel.computeInstrLatency(RISCV::XOR) +
+           SchedModel.computeInstrLatency(RISCV::SLTIU);
+  case RISCVCC::COND_NE:
+    return SchedModel.computeInstrLatency(RISCV::XOR) +
+           SchedModel.computeInstrLatency(RISCV::SLTU);
+  case RISCVCC::COND_GE:
+    return SchedModel.computeInstrLatency(RISCV::XORI) +
+           SchedModel.computeInstrLatency(RISCV::SLT);
+  case RISCVCC::COND_GEU:
+    return SchedModel.computeInstrLatency(RISCV::XORI) +
+           SchedModel.computeInstrLatency(RISCV::SLTU);
   }
 }
 
@@ -1475,41 +1480,41 @@ void RISCVInstrInfo::insertICmp(MachineBasicBlock &MBB,
   Register RHSReg = Cond[2].getReg();
 
   switch (CC) {
-    default:
-      llvm_unreachable("Unknown condition code!");
-    case RISCVCC::COND_LT:
-    case RISCVCC::COND_LTU: {
-      BuildMI(MBB, MI, DL, get(CC == RISCVCC::COND_LT ? RISCV::SLT : RISCV::SLTU),
-              DstReg)
-          .addReg(LHSReg)
-          .addReg(RHSReg);
+  default:
+    llvm_unreachable("Unknown condition code!");
+  case RISCVCC::COND_LT:
+  case RISCVCC::COND_LTU: {
+    BuildMI(MBB, MI, DL, get(CC == RISCVCC::COND_LT ? RISCV::SLT : RISCV::SLTU),
+            DstReg)
+        .addReg(LHSReg)
+        .addReg(RHSReg);
+    return;
+  }
+  case RISCVCC::COND_EQ:
+  case RISCVCC::COND_NE: {
+    Register XorReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    BuildMI(MBB, MI, DL, get(RISCV::XOR), XorReg).addReg(LHSReg).addReg(RHSReg);
+    if (CC == RISCVCC::COND_EQ) {
+      BuildMI(MBB, MI, DL, get(RISCV::SLTIU), DstReg).addReg(XorReg).addImm(1);
       return;
-    }
-    case RISCVCC::COND_EQ:
-    case RISCVCC::COND_NE: {
-      Register XorReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-      BuildMI(MBB, MI, DL, get(RISCV::XOR), XorReg).addReg(LHSReg).addReg(RHSReg);
-      if (CC == RISCVCC::COND_EQ) {
-        BuildMI(MBB, MI, DL, get(RISCV::SLTIU), DstReg).addReg(XorReg).addImm(1);
-        return;
-      } else {
-        BuildMI(MBB, MI, DL, get(RISCV::SLTU), DstReg)
-            .addReg(RISCV::X0)
-            .addReg(XorReg);
-        return;
-      }
-    }
-    case RISCVCC::COND_GE:
-    case RISCVCC::COND_GEU: {
-      Register NotCCReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-      BuildMI(MBB, MI, DL, get(CC == RISCVCC::COND_GE ? RISCV::SLT : RISCV::SLTU),
-              NotCCReg)
-          .addReg(LHSReg)
-          .addReg(RHSReg);
-      BuildMI(MBB, MI, DL, get(RISCV::XORI), DstReg).addReg(NotCCReg).addImm(1);
+    } else {
+      BuildMI(MBB, MI, DL, get(RISCV::SLTU), DstReg)
+          .addReg(RISCV::X0)
+          .addReg(XorReg);
       return;
     }
   }
+  case RISCVCC::COND_GE:
+  case RISCVCC::COND_GEU: {
+    Register NotCCReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    BuildMI(MBB, MI, DL, get(CC == RISCVCC::COND_GE ? RISCV::SLT : RISCV::SLTU),
+            NotCCReg)
+        .addReg(LHSReg)
+        .addReg(RHSReg);
+    BuildMI(MBB, MI, DL, get(RISCV::XORI), DstReg).addReg(NotCCReg).addImm(1);
+    return;
+  }
+  }
 }
 
 void RISCVInstrInfo::insertSelect(MachineBasicBlock &MBB,
@@ -1542,15 +1547,22 @@ void RISCVInstrInfo::insertSelect(MachineBasicBlock &MBB,
 }
 
 bool RISCVInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
-                                     ArrayRef<MachineOperand> Cond, Register DstReg,
-                                     Register TrueReg, Register FalseReg, int &CondCycles,
+                                     ArrayRef<MachineOperand> Cond,
+                                     Register DstReg, Register TrueReg,
+                                     Register FalseReg, int &CondCycles,
                                      int &TrueCycles, int &FalseCycles) const {
   TargetSchedModel SchedModel;
   SchedModel.init(&STI);
 
   CondCycles = getICmpCost(Cond[0].getImm(), SchedModel);
-  TrueCycles = SchedModel.computeInstrLatency(RISCV::OR) + SchedModel.computeInstrLatency(STI.hasVendorXVentanaCondOps() ? RISCV::VT_MASKC : RISCV::CZERO_EQZ);
-  FalseCycles = SchedModel.computeInstrLatency(RISCV::OR) + SchedModel.computeInstrLatency(STI.hasVendorXVentanaCondOps() ? RISCV::VT_MASKCN : RISCV::CZERO_NEZ);
+  TrueCycles = SchedModel.computeInstrLatency(RISCV::OR) +
+               SchedModel.computeInstrLatency(STI.hasVendorXVentanaCondOps()
+                                                  ? RISCV::VT_MASKC
+                                                  : RISCV::CZERO_EQZ);
+  FalseCycles = SchedModel.computeInstrLatency(RISCV::OR) +
+                SchedModel.computeInstrLatency(STI.hasVendorXVentanaCondOps()
+                                                   ? RISCV::VT_MASKCN
+                                                   : RISCV::CZERO_NEZ);
 
   return true;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index acb2c7954c..61d2d49efe 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -65,10 +65,10 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
     "riscv-min-jump-table-entries", cl::Hidden,
     cl::desc("Set minimum number of entries to use a jump table on RISCV"));
 
-static cl::opt<bool> RISCVDisableEarlyIfcvt(
-    "riscv-disable-early-ifcvt", cl::Hidden,
-    cl::desc("Disable early if-conversion"),
-    cl::init(true), cl::Hidden);
+static cl::opt<bool>
+    RISCVDisableEarlyIfcvt("riscv-disable-early-ifcvt", cl::Hidden,
+                           cl::desc("Disable early if-conversion"),
+                           cl::init(true), cl::Hidden);
 
 void RISCVSubtarget::anchor() {}
 
@@ -212,8 +212,7 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
 bool RISCVSubtarget::enableEarlyIfConversion() const {
   TargetSchedModel SchedModel;
   SchedModel.init(this);
-  return 
-    !RISCVDisableEarlyIfcvt &&
-    (hasStdExtZicond() || hasVendorXVentanaCondOps()) &&
-    SchedModel.hasInstrSchedModelOrItineraries();
+  return !RISCVDisableEarlyIfcvt &&
+         (hasStdExtZicond() || hasVendorXVentanaCondOps()) &&
+         SchedModel.hasInstrSchedModelOrItineraries();
 }

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https://github.com/llvm/llvm-project/pull/92959