[llvm] [RISCV] Do not check PostRAScheduler in enablePostRAScheduler (PR #92781)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> Don't SiFiveP400, SiFiveP600, and SiFive7 all have `let PostRAScheduler = 1;`? Why don't we need to change RISCVProcessors.td for them?

I am dumb and looked for `PostRAScheduler = 1` instead of `PostRAScheduler = true`. Will update patch.

https://github.com/llvm/llvm-project/pull/92781