[llvm] [RISCV] Do not check PostRAScheduler in enablePostRAScheduler (PR #92781)

[Craig Topper via llvm-commits]

topperc wrote:

Don't SiFiveP400, SiFiveP600, and SiFive7 all have `let PostRAScheduler = 1;`? Why don't we need to change RISCVProcessors.td for them?

https://github.com/llvm/llvm-project/pull/92781