[llvm] 3c3e71d - X86: Add regression test from issue #76416
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue May 21 11:22:24 PDT 2024
Author: Matt Arsenault
Date: 2024-05-21T20:22:17+02:00
New Revision: 3c3e71d929457daf4be425a35920cc53ed875fab
URL: https://github.com/llvm/llvm-project/commit/3c3e71d929457daf4be425a35920cc53ed875fab
DIFF: https://github.com/llvm/llvm-project/commit/3c3e71d929457daf4be425a35920cc53ed875fab.diff
LOG: X86: Add regression test from issue #76416
Also add another testcase reported at the same regression commit. Make
sure this assert is fixed when the patch is eventually reapplied.
Added:
llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
llvm/test/CodeGen/X86/issue76416.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll b/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
new file mode 100644
index 0000000000000..0e6cb7a3aff2e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; Not from issue 76416, but separate testcase reported on the same
+; regressing commit.
+define void @other_regression(i1 %cmp.not.i.i.i) {
+; CHECK-LABEL: other_regression:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movl 0, %eax
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: sarl %cl, %eax
+; CHECK-NEXT: movl $1, %edx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: shrl %cl, %edx
+; CHECK-NEXT: imull %eax, %edx
+; CHECK-NEXT: movslq %edx, %rsi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: callq *%rax
+entry:
+ br label %for.cond10.preheader
+
+trap: ; preds = %for.body13
+ unreachable
+
+for.cond10.preheader: ; preds = %while.cond.i.i.i, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ 1, %while.cond.i.i.i ]
+ %i = trunc i64 %indvars.iv to i32
+ br label %for.body13
+
+for.body13: ; preds = %for.cond10.preheader
+ %i1 = load i32, ptr null, align 4
+ %shr = ashr i32 %i1, %i
+ %shr15 = ashr i32 1, %i
+ %mul16 = mul i32 %shr15, %shr
+ %conv = sext i32 %mul16 to i64
+ call void null(ptr null, i64 %conv, ptr null)
+ br i1 false, label %while.cond.i.i.i, label %trap
+
+while.cond.i.i.i: ; preds = %while.cond.i.i.i, %for.body13
+ br i1 %cmp.not.i.i.i, label %for.cond10.preheader, label %while.cond.i.i.i
+}
diff --git a/llvm/test/CodeGen/X86/issue76416.ll b/llvm/test/CodeGen/X86/issue76416.ll
new file mode 100644
index 0000000000000..d0f7fe684a840
--- /dev/null
+++ b/llvm/test/CodeGen/X86/issue76416.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64-unknown-freebsd15.0 < %s | FileCheck %s
+
+%struct.anon.5.28.78.99.149.119 = type { [4 x i8] }
+
+ at vga_load_state_p = external dso_local global ptr, align 8
+ at vga_load_state_data = external dso_local global i8, align 1
+
+define dso_local void @vga_load_state() #0 {
+; CHECK-LABEL: vga_load_state:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jg .LBB0_3
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_2: # %for.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jle .LBB0_2
+; CHECK-NEXT: .LBB0_3: # %for.end
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB0_4: # %for.cond1
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movq vga_load_state_p(%rip), %rax
+; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movzbl (%rax,%rcx), %eax
+; CHECK-NEXT: movb %al, vga_load_state_data(%rip)
+; CHECK-NEXT: leal 1(%rcx), %eax
+; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jmp .LBB0_4
+entry:
+ %i = alloca i32, align 4
+ store i32 0, ptr %i, align 4
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %entry
+ %i1 = load i32, ptr %i, align 4
+ %cmp = icmp slt i32 %i1, 4
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body: ; preds = %for.cond
+ call void asm sideeffect "", "{ax},~{dirflag},~{fpsr},~{flags}"(i8 0) #1
+ %i2 = load i32, ptr %i, align 4
+ %inc = add nsw i32 %i2, 1
+ store i32 %inc, ptr %i, align 4
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ store i32 0, ptr %i, align 4
+ br label %for.cond1
+
+for.cond1: ; preds = %for.cond1, %for.end
+ call void asm sideeffect "", "N{dx},~{dirflag},~{fpsr},~{flags}"(i32 poison) #1
+ %i3 = load ptr, ptr @vga_load_state_p, align 8
+ %regs = getelementptr inbounds %struct.anon.5.28.78.99.149.119, ptr %i3, i32 0, i32 0
+ %i4 = load i32, ptr %i, align 4
+ %idxprom = sext i32 %i4 to i64
+ %arrayidx = getelementptr inbounds [4 x i8], ptr %regs, i64 0, i64 %idxprom
+ %i5 = load i8, ptr %arrayidx, align 1
+ store i8 %i5, ptr @vga_load_state_data, align 1
+ %i6 = load i32, ptr %i, align 4
+ %inc5 = add nsw i32 %i6, 1
+ store i32 %inc5, ptr %i, align 4
+ br label %for.cond1, !llvm.loop !0
+}
+
+attributes #0 = { "tune-cpu"="generic" }
+attributes #1 = { nounwind }
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.mustprogress"}
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