[llvm] [RISCV][GISel] Support G_{U|S}{ADD|SUB}SAT (PR #92935)

[Thorsten Schütt via llvm-commits]

tschuett wrote:

See the check line CHECK,RV32ZBB. TBH, I think the MIR tests are enough. Should I also add some codegen tests?

Up to you, but there are no assembler RISC-V files. I would change the title to Legalize.

https://github.com/llvm/llvm-project/pull/92935