[llvm] [AArch64] Lower extending sitofp using tbl (PR #92528)

[Momchil Velikov via llvm-commits]

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@@ -17840,13 +17887,39 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performVectorIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() != ISD::SINT_TO_FP || N->getValueType(0) != MVT::v4f32)
+    return SDValue();
+
+  SDNode *VASHR = N->getOperand(0).getNode();
+  if (VASHR->getOpcode() != AArch64ISD::VASHR ||
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momchil-velikov wrote:

ISel patterns forked out to https://github.com/llvm/llvm-project/pull/92922 and now require the shift to be exact.

https://github.com/llvm/llvm-project/pull/92528