[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -160,12 +166,17 @@ struct Instruction {
   const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
   const BitVector &AllDefRegs;  // The set of all aliased def registers.
   const BitVector &AllUseRegs;  // The set of all aliased use registers.
+  const BitVector &MemoryRegs;  // The set of all aliased memory use registers.
+  const BitVector
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AnastasiyaChernikova wrote:

Addressed

https://github.com/llvm/llvm-project/pull/89047