[llvm] [CodeGen] Allow mixed scalar type constraints for inline asm (PR #65465)
Dávid Ferenc Szabó via llvm-commits
llvm-commits at lists.llvm.org
Tue May 21 06:33:38 PDT 2024
https://github.com/dfszabo updated https://github.com/llvm/llvm-project/pull/65465
>From 52e62c6f6a8ecc24fd89f0ab3e55cf8db46be06c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?D=C3=A1vid=20Ferenc=20Szab=C3=B3?=
<szabodavidferenc at gmail.com>
Date: Tue, 21 May 2024 15:03:13 +0200
Subject: [PATCH] [CodeGen] Allow mixed scalar type constraints for inline asm
GCC supports code like "asm volatile ("" : "=r" (i) : "0" (f))" where i is integer type and f is floating point type. Currently this code produces an error with Clang. The change allows mixed scalar types between input and output constraints.
---
.../SelectionDAG/SelectionDAGBuilder.cpp | 8 ++-
.../CodeGen/SelectionDAG/TargetLowering.cpp | 7 ++-
llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll | 61 +++++++++++++++++++
3 files changed, 71 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index ca352da5d36eb..c27260760dadf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9322,9 +9322,11 @@ static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
MatchingOpInfo.ConstraintVT);
- if ((OpInfo.ConstraintVT.isInteger() !=
- MatchingOpInfo.ConstraintVT.isInteger()) ||
- (MatchRC.second != InputRC.second)) {
+ const bool OutOpIsIntOrFP =
+ OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.isFloatingPoint();
+ const bool InOpIsIntOrFP = MatchingOpInfo.ConstraintVT.isInteger() ||
+ MatchingOpInfo.ConstraintVT.isFloatingPoint();
+ if ((OutOpIsIntOrFP != InOpIsIntOrFP) || (MatchRC.second != InputRC.second)) {
// FIXME: error out in a more elegant fashion
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 3ec6b9b795079..17377b67ca591 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5824,8 +5824,11 @@ TargetLowering::ParseConstraints(const DataLayout &DL,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
Input.ConstraintVT);
- if ((OpInfo.ConstraintVT.isInteger() !=
- Input.ConstraintVT.isInteger()) ||
+ const bool OutOpIsIntOrFP = OpInfo.ConstraintVT.isInteger() ||
+ OpInfo.ConstraintVT.isFloatingPoint();
+ const bool InOpIsIntOrFP = Input.ConstraintVT.isInteger() ||
+ Input.ConstraintVT.isFloatingPoint();
+ if ((OutOpIsIntOrFP != InOpIsIntOrFP) ||
(MatchRC.second != InputRC.second)) {
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
diff --git a/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll b/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
new file mode 100644
index 0000000000000..d2255d9970b12
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
@@ -0,0 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr +avx < %s | FileCheck %s
+
+; The C source used as a base for generating this test:.
+
+; unsigned test(float f)
+; {
+; unsigned i;
+; // Copies f into the output operand i
+; asm volatile ("" : "=r" (i) : "0" (f));
+; return i;
+; }
+
+
+define i32 @test_int_float(float %f) {
+; CHECK-LABEL: test_int_float:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: retq
+entry:
+ %asm_call = call i32 asm sideeffect "", "=r,0,~{dirflag},~{fpsr},~{flags}"(float %f)
+ ret i32 %asm_call
+}
+
+define i32 @test_int_ptr(ptr %f) {
+; CHECK-LABEL: test_int_ptr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: retq
+entry:
+ %asm_call = call i32 asm sideeffect "", "=r,0,~{dirflag},~{fpsr},~{flags}"(ptr %f)
+ ret i32 %asm_call
+}
+
+define i64 @test_int_vec(<4 x i16> %v) {
+; CHECK-LABEL: test_int_vec:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: retq
+entry:
+ %asm_call = call i64 asm sideeffect "", "=v,0,~{dirflag},~{fpsr},~{flags}"(<4 x i16> %v)
+ ret i64 %asm_call
+}
+
+define <4 x i32> @test_int_vec_float_vec(<4 x float> %f) {
+; CHECK-LABEL: test_int_vec_float_vec:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: retq
+entry:
+ %asm_call = call <4 x i32> asm sideeffect "", "=v,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %f)
+ ret <4 x i32> %asm_call
+}
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