[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -166,6 +166,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
   BitVector ImplUseRegs = RATC.emptyRegisters();
   BitVector AllDefRegs = RATC.emptyRegisters();
   BitVector AllUseRegs = RATC.emptyRegisters();
+  BitVector MemoryRegs = RATC.emptyRegisters();
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AnastasiyaChernikova wrote:

Not currently used, it was added in addition to NotMemoryRegs since they are all aliased registers together.

https://github.com/llvm/llvm-project/pull/89047