[llvm] [RISCV] Unify getDemanded between forward and backwards passes in RISCVInsertVSETVLI (PR #92860)

[Luke Lau via llvm-commits]

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@@ -1940,8 +1940,9 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
 ; RV64ZVE32F-NEXT:    vmv.x.s a2, v10
 ; RV64ZVE32F-NEXT:    slli a2, a2, 2
 ; RV64ZVE32F-NEXT:    add a2, a0, a2
-; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV64ZVE32F-NEXT:    vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
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lukel97 wrote:

This is an example of where eagerly emitting x0,x0 vsetvlis prevents coalescing. I have a plan to fix this in #89089 

https://github.com/llvm/llvm-project/pull/92860