[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Jun Wang via llvm-commits]

================
@@ -121,6 +127,15 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
                         const CCValAssign &VA) override {
     markPhysRegUsed(PhysReg);
 
+    if (VA.getLocVT() == MVT::i1) {
+      MIRBuilder.buildCopy(ValVReg, PhysReg);
+      MRI.setRegClass(ValVReg, MIRBuilder.getMF()
+                                   .getSubtarget<GCNSubtarget>()
+                                   .getRegisterInfo()
+                                   ->getBoolRC());
----------------
jwanggit86 wrote:

If I dont' do that, RegBankSelect will produce undesirable results in at least the following 2 cases:

Case 1: i1 arg is stored to memory.
After IRSelector:
```
%0:_(s1) = COPY $sgpr4_sgpr5
%1:_(p1) = G_IMPLICIT_DEF
G_STORE %0:_(s1), %1:_(p1) :: (store (s1) into
  `ptr addrspace(1) undef`, addrspace 1)
```
After RegBankSelect:
```
%0:sgpr(s1) = COPY $sgpr4_sgpr5
%1:sgpr(p1) = G_IMPLICIT_DEF
%2:sgpr(s32) = G_ZEXT %0:sgpr(s1)
%5:vgpr(s32) = COPY %2:sgpr(s32) // result of ZEXT
                                 // copied to a vgpr
%6:vgpr(p1) = COPY %1:sgpr(p1)
G_STORE %5:vgpr(s32), %6:vgpr(p1) :: (store (s8)
  into `ptr addrspace(1) undef`, addrspace 1)
```
After InstructionSelect:
```
%0:sreg_32 = COPY $sgpr4_sgpr5 //will cause "illegal copy" later
  %1:sreg_64 = IMPLICIT_DEF
  %2:sreg_32 = S_AND_B32 %0:sreg_32, 1, implicit-def dead $scc
  %5:vgpr_32 = COPY %2:sreg_32
  %6:vreg_64 = COPY %1:sreg_64
  GLOBAL_STORE_BYTE %6:vreg_64, %5:vgpr_32, 0, 0, implicit $exec
    :: (store (s8) into `ptr addrspace(1) undef`, addrspace 1)
```

https://github.com/llvm/llvm-project/pull/72461