[llvm] [RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (PR #92768)

[Michael Maitland via llvm-commits]

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@@ -1677,8 +1677,9 @@ let Predicates = [HasVInstructions] in {
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
 def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
-                      SchedBinaryMC<"WriteVRGatherVV", "ReadVRGatherVV_data",
-                                    "ReadVRGatherVV_index">;
+                      SchedBinaryMC<"WriteVRGatherVVEEW",
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michaelmaitland wrote:

What do you think about `VPseudoVGTR_VV_EEW<int eew, ...>` -> `VPseudoVGTREI16_VV<int eew, ...>`

https://github.com/llvm/llvm-project/pull/92768